Xstream - A hardware accelerator for digital holographic imaging

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn , Issue , 2005, Pages

  Lenart, Thomas ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; IMAGE PROCESSING; IMAGE RECONSTRUCTION; MATHEMATICAL TRANSFORMATIONS; REPAIR; RESTORATION; SENSORS;

CELL LIBRARIES; CUSTOM DESIGNS; DIGITAL IMAGE SENSORS; EXTERNAL-; FPGA PLATFORMS; FRAMES PER SECONDS; HARDWARE ACCELERATORS; HOLOGRAPHIC IMAGING; INTERLEAVED MEMORIES; MEMORY CONTROLLERS; MICRO-PROCESSORS; PROPOSED ARCHITECTURES; REAL-TIME PERFORMANCES; RECONSTRUCTION ALGORITHMS; VISIBLE IMAGES;

DATA STORAGE EQUIPMENT;

EID: 56749182783     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2005.4633556     Document Type: Conference Paper

References (9)

1. U. Schnars and W. Jueptner, Digital Holography. Springer-Verlag, Berlin, Heidelberg: Springer, 2005.
2. M. Gustafsson, M. Sebesta, B. Bengtsson, S.-G. Pettersson, P. Egelberg, and T. Lenart, "High resolution digital transmission microscopy - a Fourier holography approach," Optics and Lasers in Engineering, vol. 41(3), pp. 553-563, Mar. 2004.
3. B. Parhami, Computer Arithmetic. 198 Madison Avenue, New York 10016: Oxford University Press, 2000.
4. T. Lenart and V. Öwall, "A 2048 complex point FFT processor using a novel data scaling approach," in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'03), Bangkok, Thailand, May 25-28 2003, pp. 45-48.
5. S. He, "Concurrent VLSI Architectures for DFT Computing and Algorithms for Multi-output Logic Decomposition," Ph.D. dissertation, Ph.D. dissertation, Lund University, Department of Applied Electronics, 1995.
6. ARM Ltd., "AMBA Specification - Advanced Microcontroller Bus Architecture," http://www.arm.com, 1999.
7. MT48LC32M16A2-75, "Micron Technology - SDRAM components," http://www.micron.com.
8. N. Miyamoto, L. Karnan, K. Maruo, K. Kotani, and T. Ohmi1, "A Small-Area High-Performance 512-Point 2-Dimensional FFT Single-Chip Processor," in Proc. of European Solid-State Circuits (ESSCIRC'03), Estoril, Portugal, Sept. 16-18 2003, pp. 603-606.
9. I. Uzun, A. Amira, and F. Bensaali, "A reconfigurable co-processor for high-resolution image filtering in real time," in Proc. of the 10th IEEE International Conference on Electronics, Circuits and Systems, Sharjah, United Arab Emirates, Dec. 14-17 2003, pp. 192-195.