Scheduling semiconductor manufacturing processes to enhance system identification

Journal of Process Control

Volumn 18, Issue 10, 2008, Pages 946-953

  Pasadyn, Alexander J ^a   Lee, Hyung ^a   Edgar, Thomas F ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Batch scheduling; Equipment allocation; Sampling plan; Semiconductor manufacturing

Indexed keywords

CONTROL THEORY; ELECTRIC CONDUCTIVITY; MANUFACTURE; SAMPLING; SCHEDULING; SEMICONDUCTOR MATERIALS;

BATCH SCHEDULING; CONTROL ALGORITHMS; CONTROL APPLICATIONS; DATA SETS; EQUIPMENT ALLOCATION; EQUIPMENT ALLOCATIONS; FACTORY SCHEDULES; INFORMATION CONTENTS; MANUFACTURING LINES; MULTIPLE PROCESSING; OUTPUT PERFORMANCES; SAMPLING PLAN; SAMPLING PLANS; SEMICONDUCTOR MANUFACTURING; SEMICONDUCTOR MANUFACTURING PROCESSES; SIMULATION RESULTS; SOURCES OF VARIATIONS; STATE ERRORS; SYSTEM IDENTIFICATIONS;

COVARIANCE MATRIX;

EID: 56349137609     PISSN: 09591524     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jprocont.2008.04.011     Document Type: Article

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