Analyzing the impact of data prefetching on chip multiprocessors

13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008

Volumn , Issue , 2008, Pages

  Fukumoto, Naoto ^a   Mihara, Tomonobu ^a   Inoue, Koji ^a   Murakami, Kazuaki ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS; DATA TRANSFER; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; SYSTEMS ANALYSIS;

CACHE BLOCKS; CORE PROCESSORS; DATA PREFETCHING; IN CHIPS; L2 CACHES; MEMORY PERFORMANCES; ON CHIPS; PREFETCH; PREFETCHES; PREFETCHING; PREFETCHING TECHNIQUES; PROCESSOR CHIPS; PROGRAM EXECUTIONS; SHARED RESOURCES;

COMPUTER ARCHITECTURE;

EID: 55849118080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCSAC.2008.4625454     Document Type: Conference Paper

References (6)

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2. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-oriented Full-system Simulation Using M5. In Proceedings of the Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads, February 2003.
3. N. D. Enright Jerger, E. L. Hill, and M. H. Lipasti. Friendly Fire: Understanding the Effects of Multiprocessor Prefetching. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, March 2006.
4. A. J. Smith. Cache Memories. Computing Surveys, Vol. 14, No.3, September 1982.
5. V. Srinivasan, E. S. Davidson, and G. S. Tyson. A Prefetch Taxonomy. IEEE Transactions on Computers, Vol.53, No.2, February 2004.
6. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, June 1995.