Outer loop pipelining for application specific datapaths in FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 10, 2008, Pages 1268-1280

  Turkington, Kieron ^a   Constantinides, George A ^a,c   Masselos, Konstantinos ^b,c   Cheung, Peter Y K ^a,c  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PELOPONNESE   (Greece)

^c IEEE

Author keywords

Field programmable gate array (FPGA); Integer linear programming (ILP); Nested loop; Pipelining

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM COMPILERS; TESTING;

ALTERA STRATIX; APPLICATION-SPECIFIC; COMPILE-TIME; DATA-PATHS; FIELD-PROGRAMMABLE GATE ARRAY (FPGA); HARDWARE CO-PROCESSORS; HARDWARE COMPILERS; INTEGER LINEAR PROGRAMMING (ILP); LOOP LEVEL; LOOP PIPELINING; NESTED LOOP; OUTER LOOP; PIPELINING; PROGRAMMABLE GATE-ARRAY; SOFTWARE PIPELINING;

STATISTICAL TESTS;

EID: 52649171941     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2001744     Document Type: Conference Paper

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