Symbolic compilation of PSL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 10, 2008, Pages 1737-1750

  Cimatti, Alessandro ^a   Roveri, Marco ^a   Tonetta, Stefano ^a  

^a ITC IRST   (Italy)

Author keywords

Binary decision diagram (BDD); B chi Automata; Formal methods; Formal verification; Property Specification Language (PSL); Satisfiability (SAT); Sequential Extended Regular Expressions (SEREs); Symbolic compilation

Indexed keywords

INFORMATION THEORY; SPECIFICATION LANGUAGES; STANDARDS; STATE SPACE METHODS; TEMPORAL LOGIC;

ANALYSIS TOOLS; BINARY DECISION DIAGRAM (BDD); EXPERIMENTAL ANALYSIS; FORMAL METHODS; FORMAL VERIFICATION; HARDWARE DESIGNS; LINEAR-TEMPORAL LOGIC; LOW COSTS; NORMAL FORM; PROPERTY SPECIFICATION LANGUAGE; PROPERTY SPECIFICATION LANGUAGE (PSL); SATISFIABILITY (SAT); SEARCH TIME; SEQUENTIAL EXTENDED REGULAR EXPRESSIONS; SEQUENTIAL EXTENDED REGULAR EXPRESSIONS (SERES); STATE SPACES; SYMBOLIC COMPILATION; SYNTACTIC TRANSFORMATIONS;

ERROR ANALYSIS;

EID: 52649130299     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2003303     Document Type: Article

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