Low VT metal-gate/high-k nMOSFETs - PBTI dependence and VT tune-ability on La/Dy-capping layer locations and laser annealing conditions

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 62-63

  Chang, S Z ^b   Hoffmann, T Y ^a   Yu, H Y ^c   Aoulaiche, M ^d   Rohr, E ^a   Adelmann, C ^a   Kaczer, B ^a   Delabie, A ^a   Favia, P ^a   Van Elshocht, S ^a   Kubicek, S ^a   Scharm, T ^a   Witters, T ^a   Ragnarsson, L A ^a   Wang, X P ^a   Cho, H J ^e   Mueller, M ^f   Chiarella, T ^a   Absil, P ^a   Biesemans, S ^a  

^a IMEC   (Singapore)

^b TSMC   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d UNIVERSITY OF LEUVEN   (Belgium)

^e Samsung   (Belgium)

^f NXP TSMC Research Center   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

METALS;

N-MOSFETS; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 51949091876     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588564     Document Type: Conference Paper

References (10)

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3. V. Narayanan et al., Tech. VLSI, 22.2 (2006);
4. B. H. Lee et al., IEDM, p.859 (2004);
5. B. J. O' Sullivan et al., SSDM, p.372 (2007);
6. S.Z. Chang et al., submitted to EDL;
7. B. Kaczer et al., Tech. IRPS, p. 381 (2005);
8. P. Sivasubramani et al., Tech. VLSI, p.68 (2007);
9. L. -A. Ragnarsson et al., EDL, Vol. 28, NO.6, p. 486 (2007);
10. C. Shen et al., IEDM, p. 733 (2004)