Partial reconfiguration bitstream compression for Virtex FPGAs

Proceedings - 1st International Congress on Image and Signal Processing, CISP 2008

Volumn 5, Issue , 2008, Pages 183-185

  Gu, Haiyun ^a   Chen, Shurong ^a  

^a SHANGHAI MARITIME UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSION RATIO (MACHINERY); DATA COMPRESSION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SIGNAL PROCESSING;

BITSTREAM COMPRESSION; BITSTREAMS; COMPRESSION RATIOS; INTERNATIONAL CONGRESSES; MODULE-BASED; PARTIAL RECONFIGURATION; REAL-WORLD APPLICATIONS; THREE-LEVEL; VIRTEX FPGAS;

ADAPTIVE ALGORITHMS;

EID: 51849147931     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CISP.2008.253     Document Type: Conference Paper

References (4)

1. A. Dandalis, V. K. Prasanna. "Configuration Compression for FPGA-based Embedded Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13 (12), December 2005, pp. 1394-1398.
2. Zhiyuan Li, Scott H., "Configuration Compression for Virtex FPGAs", IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society Washington, DC, USA, 2001, pp. 147 - 159.
3. Lei He, T. Mitra, and Weng-Fai Wong, "Configuration bitstream compression for dynamically reconfigurable FPGAs", Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, November 07-11, 2004, pp.766-773.
4. Xilinx reference guide, "Two flows for partial reconfiguration: Module based or difference based", Application Note 290, Xilinx, 2004