Understanding the optimization of sub-45nm FinFET devices for ESD applications

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 2007, Pages

  Tremouilles D ^a,e   Thijs, S ^b   Russ, C ^c   Schneider, J ^c   Duvvury, C ^d   Collaert, N ^a   Linten, D ^a   Scholz, M ^a   Jurczak, M ^a   Gossner, H ^c   Groeseneken, G ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d TEXAS INSTRUMENTS   (United States)

^e LAAS CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATIC DISCHARGE; EPITAXIAL GROWTH; GATES (TRANSISTOR); SILICIDES;

DEVICE LAYOUTS; ESD PERFORMANCE; FIN WIDTHS; FINFET DEVICES; FINFETS; GATE LENGTHS; OPERATION MODES; SELECTIVE EPITAXIAL GROWTHS; TCAD SIMULATIONS;

ELECTROSTATIC DEVICES;

EID: 51849141785     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EOSESD.2007.4401780     Document Type: Conference Paper

References (5)

1. C. Russ et al, "ESD Evaluation of the Emerging MUGFET Technology", EOS/ESD Symposium, pp. 280-289, 2005.
2. H. Gossner et al, "Unique ESD failure mechanism in a MuGFET technology", IEDM Tech. Dig., 2006.
3. K. Bock et al, "Influence of well profile and gate length on the ESD performance of a fully silicided 0.25um technology", EOS/Symposium, pp. 308-315, 1997.
4. B. Keppens et al, "Concept for body coupling in SOI MOS transistor to improve multi-finger triggering", EOS/ESD Symposium, pp. 172-178, 2006.
5. J. Kedzierski et al, "Extension and Source/Drain Design for High Performance FinFET Devices", IEEE Trans. on Electron Dev., vol. 50, no. 4, pp. 952-958, 2003