Scalable statistical measurement and estimation of a mm wave CML static divider sensitivity in 65nm SOI CMOS

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2008, Pages 625-628

  Kim, Daeik D ^a   Cho, Ongyeun ^a   Kim, Jonghae ^a  

^a IBM RESEARCH   (United States)

Author keywords

65nm SOI CMOS; Mm wave CML static divider; Scalable measurement and statistical performance estimation; Sensitivity curve, process induced variation

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; ESTIMATION; INTEGRATED CIRCUITS; RADIO WAVES; SILICON WAFERS; STANDARDS; STATISTICAL METHODS;

65NM SOI CMOS; ANALYTIC MODELING; CURVE ESTIMATION; MM WAVE CML STATIC DIVIDER; MM WAVES; RADIO FREQUENCY INTEGRATED CIRCUITS; RF MEASUREMENTS; SCALABLE MEASUREMENT AND STATISTICAL PERFORMANCE ESTIMATION; SENSITIVITY CURVE, PROCESS-INDUCED VARIATION; SOI CMOS; STANDARD VARIATION;

SENSITIVITY ANALYSIS;

EID: 51849133656     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2008.4561515     Document Type: Conference Paper

References (5)

1. C. Cho, et al., "Decomposition and analysis of process variability using constrained principal component analysis," Trans. Semicond. Manuf., vol. 21, no. 1, pp. 55-62.
2. E. Laskin, et al., "Low-power, low-phase noise SiGe HBT static frequency divider topologies up to 100 GHz," BCTM, pp. 1-4, 2006.
3. J.-O. Plouchart, et al., "Performance variations of a 66GHz static CML divider in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 526-527, 2006.
4. D. Lim, et al., "Performance variability of a 90GHz static CML frequency divider in 65nm SOI CMOS," ISSCC Dig. Tech. Papers, pp. 542-543, 2006.
5. U. Singh, et al., "High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz," J. Solid-State Circuits, vol. 40, no. 8, pp. 1658-1661.