A parallel transitive closure computation algorithm for VLSI test generation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2367, Issue , 2002, Pages 243-252

  Bawa, Seema ^a,b   Sharma, G K ^a,b  

^a THAPAR UNIVERSITY   (India)

^b IIITM   (India)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BALANCING; DISTRIBUTED COMPUTER SYSTEMS; VLSI CIRCUITS;

ALGORITHM DEVELOPMENT; DISTRIBUTED COMPUTING ENVIRONMENT; ISO-EFFICIENCY FUNCTIONS; LOAD BALANCING TECHNIQUE; PARALLEL VIRTUAL MACHINES; PERFORMANCE METRICS; POLYLOGARITHMIC TIME; TRANSITIVE CLOSURE COMPUTATIONS;

COMPUTATIONAL EFFICIENCY;

EID: 51749104656     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48051-x_25     Document Type: Conference Paper

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