Analysis and performance evaluation of area-efficient true random bit generators on FPGAs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 1572-1575

  Alioto, Massimo ^a   Fondelli, Luca ^a   Rocchi, Santina ^a  

^a UNIVERSITY OF SIENA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

NUMBER THEORY; RANDOM PROCESSES; TECHNICAL PRESENTATIONS;

INTERNATIONAL SYMPOSIUM; LOW AREA; RANDOM BIT GENERATORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 51749092414     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541732     Document Type: Conference Paper

References (10)

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