Transport properties of the SiO(2)/Ta(2)O(5) stack as gate dielectric in CMOS processes

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 152-155

  Devoivre, T ^a,b   Papadas, C ^a   Ghibaudo, G ^b   Pananakakis, G ^b   Setton, M ^c   Sandler, N ^d  

^a STMICROELECTRONICS   (Italy)

^b Grenoble INP Phelma   (France)

^c Lam Research Sarl   (France)

^d LAM RESEARCH CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS;

CMOS PROCESSS; CONDUCTION MECHANISM; CONDUCTION MODE; NEGATIVE BIAS; POOLE-FRENKEL MECHANISMS; POSITIVE GATE BIAS; SCHOTTKY;

TANTALUM OXIDES;

EID: 51549120427     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. T. Devoivre, C. Papadas, M. Sellon, N. Sandler, L. Vallier and I. Bourras, ASMC, Boston, September 1998.
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5. DeSalvo et ai, 9th Int. Workshop on Thin Film Dielectrics, Toulouse, March 1998.
6. P. Hesto in "Instabilities in silicon devices", Barhollin O. and A. Vapaille, Editors, Elsevier Science Puhlishers B. V., Amsterdam, 1986, p. 263.
7. G. Pananakakis, G. Ghibaudo, R. Kies and C. Papadas, J. Appl. Phys., Vol. 78, No 4, August 1995, pp. 2635-2641.