Package reliability using μPILR™ in stacking and flip chip

Proceedings - 2007 International Symposium on Microelectronics, IMAPS 2007

Volumn , Issue , 2007, Pages 1168-1176

  Banijamali, Bahareh ^a   Mohammed, Ilyas ^a  

^a Tessera Inc   (United States)

Author keywords

PILR; Copper micro bumps; CSP; Flip chip; Pitch; Stacking

Indexed keywords

CSP; FLIP CHIP; MICRO-BUMPS; PITCH; STACKING;

CHIP SCALE PACKAGES; COPPER; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; MICROELECTRONICS; MINIATURE INSTRUMENTS; RELIABILITY; SOLDERING;

LOADING;

EID: 51349088220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Moran S P, Solberg V, Wade C P, "MicroContact CSP", Advanced Packaging, Jan 2007.
2. Solberg V, "μPILR Package-on-package qualification testing", SMTA IWLPC, Sep 2007.
3. Solberg V, "Low profile NAND flash stacked package-on-package", Draft-SMTA International, Oct 2007.
4. Damberg P, Gray G, Moran S P, Solberg V, "Mobile and wireless packaging solutions", Semiconductor International, Aug 2007.
5. JEDEC Standard JESD22-B111, Board level drop test method of components for handheld electronic products, 2003.
6. Zhao J, Garner L J, "Mechanical modeling and analysis of board level drop test of electronic package", Intel Technology Journal, 2006.