CMOS performance enhancement in hybrid orientation technologies

Journal of Computational Electronics

Volumn 7, Issue 3, 2008, Pages 181-186

  Maiti, Tapas Kumar ^a   Mahato, Satyasopan ^a   Chakraborty, Pinaki ^a   Maiti, Chinmay Kumar ^a   Sarkar, Subir Kumar ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b JADAVPUR UNIVERSITY   (India)

Author keywords

CMOS integrated circuits; Hybrid Orientation Technology; Mobility; Process induced strain; Strained Si; Technology CAD

Indexed keywords

COMPUTER NETWORKS; PROCESS ENGINEERING;

CMOS INTEGRATED CIRCUITS; HYBRID ORIENTATION TECHNOLOGY; MOBILITY; PROCESS-INDUCED STRAIN; STRAINED-SI; TECHNOLOGY CAD;

TECHNOLOGY;

EID: 50949096007     PISSN: 15698025     EISSN: 15728137     Source Type: Journal    
DOI: 10.1007/s10825-008-0244-0     Document Type: Article

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