An embedded reconfigurable logic core based on variable grain logic cell architecture

ICFPT 2007 - International Conference on Field Programmable Technology

Volumn , Issue , 2007, Pages 241-244

  Satou, Yoshiaki ^a   Amagasaki, Motoki ^a   Miura, Hiroshi ^a   Matsuyama, Kazunori ^a   Yamaguchi, Ryoichi ^a   Iida, Masahiro ^a   Sueyoshi, Toshinori ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BENCHMARKING; CARRY LOGIC; DELAY CIRCUITS; LOGIC CIRCUITS; LOGIC DEVICES;

APPLICATIONS.; BASIC LOGIC; BENCHMARK CIRCUITS; COARSE-GRAINED; CONFIGURATION MEMORY; CRITICAL PATH DELAYS; DSP BENCHMARKS; INTERNATIONAL CONFERENCES; KEY FEATURE; OPERATION SPEEDS; RE-CONFIGURABLE COMPUTING; RECONFIGURABLE LOGIC; RIPPLE CARRY ADDER; TECHNOLOGY-MAPPING; VARIABLE GRAIN LOGIC CELL;

TECHNOLOGY;

EID: 50249189278     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2007.4439256     Document Type: Conference Paper

References (11)

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