Evaluation of variable grain logic cell architecture for reconfigurable device

IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip

Volumn , Issue , 2006, Pages 198-203

  Amagasaki, Motoki ^a   Shimokawa, Takurou ^a   Matsuyama, Kazunori ^a   Yamaguchi, Ryoichi ^a   Nakayama, Hideaki ^a   Hamabe, Naoto ^a   Iida, Masahiro ^a   Sueyoshi, Toshinori ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BALANCE (WEIGHTING); BASIC LOGIC; BIT MULTIPLIER; COARSE GRAINED (CG); CONFIGURATION MEMORY; CRITICAL PATH DELAYS; DEVICE SPEED; GENERAL (CO); IN ORDER; INTERNATIONAL CONFERENCES; LOGIC CELLS; OPERATION SPEEDS; RECONFIGURABLE DEVICES; RECONFIGURABLE LOGIC (RL); RIPPLE CARRY ADDER (RCA); SYSTEM ON CHIP (SOCS); VARIABLE GRAIN LOGIC CELL; VERY LARGE SCALE INTEGRATION (VLSI);

ADDERS; AGRICULTURAL PRODUCTS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURE; CARRY LOGIC; CELLS; CMOS INTEGRATED CIRCUITS; FUZZY LOGIC; INTEGRATED CIRCUITS; LOGIC CIRCUITS; LSI CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

LOGIC DEVICES;

EID: 34548132336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2006.313233     Document Type: Conference Paper

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