Automated refinement checking of concurrent systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 318-325

  Kundu, Sudipta ^a   Lerner, Sorin ^a   Gupta, Rajesh ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED THEOREM PROVING; COMMUNICATING SEQUENTIAL PROCESSES; COMPUTER-AIDED DESIGN; CONCURRENT PROCESSING; CONCURRENT SYSTEMS; CURRENT STATE; ENGINEERING CHANGE ORDERS; HARDWARE AND SOFTWARE; HIGH-LEVEL SPECIFICATIONS; INDUSTRIAL CASE STUDIES; INFINITE STATE SPACE; INFINITE STATES; INTERNATIONAL CONFERENCES; POST-SYNTHESIS MODIFICATION; REFINEMENT CHECKING; STEPWISE REFINEMENT; TRANSLATION VALIDATION;

AUTOMATA THEORY; AUTOMATION; COMPUTER OPERATING PROCEDURES; COMPUTER SOFTWARE; DESIGN; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; PROGRAM TRANSLATORS; SPECIFICATIONS; STATE SPACE METHODS; TECHNOLOGY; THEOREM PROVING;

CONCURRENCY CONTROL;

EID: 50249165432     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397284     Document Type: Conference Paper

References (34)

1. EP2. www.eftpos2000.ch.
2. Failures-divergence refinement: FDR2 user manual. Formal Systems (Europe) Ltd., Oxford, England, June 2005.
3. T. Ball, R. Majumdar, T. Millstein, and S. K. Rajamani. Automatic predicate abstraction of C programs. In Proceedings PLDI 2001, June 2001.
4. Nick Benton. Simple relational correctness proofs for static analyses and program transformations. In POPL 2004, January 2004.
5. A. Benveniste, L. Carloni, P. Caspi, and A. Sangiovanni-Vincentelli. Heterogeneous reactive systems modeling and correct-by-construction deployment, 2003.
6. 20 states and beyond. In Proceedings of UCS 1990, 1990.
7. Doran Bustan and Orna Grumberg. Simulation based minimization. In David A. McAllester, editor, CADE 2000, volume 1831 of LNCS, pages 255-270. Springer Verlag, 2000.
8. S. Chaki, E. Clarke, J. Ouaknine, N. Sharygina, and N. Sinha. Concurrent software verification with states, events and deadlocks. Formal Aspects of Computing Journal, 17(4):461-483, December 2005.
9. E. M. Clarke and David E. Long Orna Grumberg. Verification tools for finite-state concurrent systems. In A Decade of Concurrency, Reflections and Perspectives, volume 803 of LNCS. Springer Verlag, 1994.
10. C.N. Ip and D.L. Dill. Better verification through symmetry. In D. Agnew, L. Claesen, and R. Camposano, editors, Computer Hardware Description Languages and their Applications, pages 87-100, Ottawa, Canada, 1993. Elsevier Science Publishers B.V., Amsterdam, Netherland.
11. D. Detlefs, G. Nelson, and J. B. Saxe. Simplify: A theorem prover for program checking. Journal of the Association for Computing Machinery, 52(3):365-473, May 2005.
12. B. Dutertre and S. Schneider. Using a PVS embedding of CSP to verify authentication protocols. In TPHOL 97, Lecture Notes in Artificial Intelligence. Springer-Verlag, 1997.
13. Susanne Graf and Hassen Saidi. Construction of abstract state graphs of infinite systems with PVS. In CAV 97, June 1997.
14. Thomas A. Henzinger, Ranjit Jhala, Rupak Majumdar, and Gregoire Sutre. Lazy abstraction. In POPL 2002, January 2002.
15. C. A. R. Hoare. Communicating Sequential Processes. Prentice Hall International, 1985.
16. Yoshinao Isobe and Markus Roggenbach. A generic theorem prover of CSP refinement. In TACAS '05, volume 1503 of Lecture Notes in Computer Science (LNCS), pages 103-123. Springer-Verlag, April 2005.
17. Mark B. Josephs. A state-based approach to communicating processes. Distributed Computing, 3(1):9-18, March 1988.
18. Moshe Y. Vardi Kathi Fisler. Bisimulation and model checking. In Proceedings of the 10th Conference on Correct Hardware Design and Verification Methods, Bad Herrenalb Germany CA, September 1999.
19. Sudipta Kundu, Sorin Lerner, and Rajesh Gupta. Automated refinement checking of concurrent systems. Technical report, University of California, San Diego, 2007. http://mesl.ucsd.edu/pubs/ iccad07-tr.pdf.
20. David Lacey, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. Proving correctness of compiler optimizations by temporal logic. In POPL 2002, January 2002.
21. Edward A. Lee and Alberto L. Sangiovanni-Vincentelli. A framework for comparing models of computation. IEEE Trans. on CAD of Integrated Circuits and Systems, 17(12): 1217-1229, 1998.
22. Stan Liao, Steve Tjiang, and Rajesh Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment. In DAC '97: Proceedings of the 34th annual conference on Design automation, pages 70-75, New York, NY, USA, 1997. ACM Press.
23. Panagiotis Manolios, Kedar S. Namjoshi, and Robert Summers. Linking theorem proving and model-checking with well-founded bisimulation. In CAV '99: Proceedings of the 11th International Conference on Computer Aided Verification, pages 369-379, London, UK, 1999. Springer-Verlag.
24. Panagiotis Manolios and Sudarshan K. Srinivasan. Automatic verification of safety and liveness for xscale-like processor models using web refinements. In DATE '04: Proceedings of the conference, on Design, automation and test in Europe, page 10168, Washington, DC, USA, 2004. IEEE Computer Society.
25. K. L. McMillan. A methodology for hardware verification using compositional model checking. Sci. Comput. Program., 37(1-3):279-309, 2000.
26. George C. Necula. Translation validation for an optimizing compiler. In PLDI 2000, June 2000.
27. S. Owre, J.M. Rushby, and N. Shankar. PVS: A prototype verification system. In CADE 92. Springer-Verlag, 1992.
28. L. C. Paulson. Isabelle: A generic theorem prover, volume 828 of Lecure Notes in Computer Science. Springer Verlag, 1994.
29. D. Peled. Ten years of partial order reduction. In CAV 98, June 1998.
30. A. Pnueli, M. Siegel, and E. Singerman. Translation validation. In TACAS '98, volume 1384 of Lecture Notes in Computer Science, pages 151-166, 1998.
31. 20 dining philosophers for deadlock. In TACAS '95, 1995.
32. Ingo Sander and Axel Jantsch. System modeling and transformational design refinement in forsyde [formal system design]. IEEE Trans. on CAD of Integrated Circuits and Systems, 23(1): 17-32, 2004.
33. J. P. Talpin, P. L. Guernic, S. K. Shukla, F. Doucet, and R. Gupta. Formal refinement checking in a system-level design methodology. Fundamenta Informaticae, 62(2):243-273, 2004.
34. H. Tej and B.Wolff. A corrected failure-divergence model for CSP in Isabelle/HOL. In FME 97, 1997.