-
1
-
-
25844521523
-
A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling
-
M. Chen and R. Brodersen, "A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling," IEICE Trans. Electronics, vol. E88-C, no. 6, pp. 1114-1121, 2005.
-
(2005)
IEICE Trans. Electronics
, vol.E88-C
, Issue.6
, pp. 1114-1121
-
-
Chen, M.1
Brodersen, R.2
-
2
-
-
42549086692
-
A Flexible Low Power Sub-sampling UWB Receiver Based on Line Spectrum Estimation Methods
-
Y. Vanderperren, W. Dehaene, and G. Leus, "A Flexible Low Power Sub-sampling UWB Receiver Based on Line Spectrum Estimation Methods," in Proc. IEEE Int. Conf. on Comm., 2006.
-
(2006)
Proc. IEEE Int. Conf. on Comm
-
-
Vanderperren, Y.1
Dehaene, W.2
Leus, G.3
-
3
-
-
29044431930
-
Timing Acquisition in Ultra-wideband Communication Systems
-
S. Aedudodla, S. Vijayakumaran, and T. Wong, "Timing Acquisition in Ultra-wideband Communication Systems," IEEE Trans. Vehic. Tech., vol. 54, no. 5, pp. 1570-1583, 2005.
-
(2005)
IEEE Trans. Vehic. Tech
, vol.54
, Issue.5
, pp. 1570-1583
-
-
Aedudodla, S.1
Vijayakumaran, S.2
Wong, T.3
-
5
-
-
33846840897
-
Blind Synchronization in Asynchronous UWB Networks Based on the Transmit-Reference Scheme
-
R. Djapic, G. Leus, A.-J. van der Veen, and A. Trindade, "Blind Synchronization in Asynchronous UWB Networks Based on the Transmit-Reference Scheme," EURASIP J. Wireless Comm. Netw., 2006.
-
(2006)
EURASIP J. Wireless Comm. Netw
-
-
Djapic, R.1
Leus, G.2
van der Veen, A.-J.3
Trindade, A.4
-
6
-
-
28844506779
-
Timing Ultra-Wideband Signals with Dirty Templates
-
L. Yang and G. Giannakis, "Timing Ultra-Wideband Signals with Dirty Templates," IEEE Trans. Comm., vol. 53, no. 11, pp. 1952 - 1963, 2005.
-
(2005)
IEEE Trans. Comm
, vol.53
, Issue.11
, pp. 1952-1963
-
-
Yang, L.1
Giannakis, G.2
-
7
-
-
33847356761
-
Synchronization of Ultra-Wideband Signals in the Dense Multipath Channel,
-
Ph.D. dissertation, Univ. Southern Calif
-
E. Homier, "Synchronization of Ultra-Wideband Signals in the Dense Multipath Channel," Ph.D. dissertation, Univ. Southern Calif., 2004.
-
(2004)
-
-
Homier, E.1
-
8
-
-
41649083689
-
Low-Complexity Subspace Methods for Channel Estimation and Synchronization in Ultra-Wideband Systems
-
I. Maravić and M. Vetterli, "Low-Complexity Subspace Methods for Channel Estimation and Synchronization in Ultra-Wideband Systems," in Int. Workshop on UWB Systems, 2003.
-
(2003)
Int. Workshop on UWB Systems
-
-
Maravić, I.1
Vetterli, M.2
-
9
-
-
26944436289
-
Principal Components Tracking Algorithms for Synchronization and Channel Identification in UWB Systems
-
J. Zhang et al., "Principal Components Tracking Algorithms for Synchronization and Channel Identification in UWB Systems," in IEEE 8th Int. Symp. Spread Spectrum Tech. and Appl., 2004, pp. 369-373.
-
(2004)
IEEE 8th Int. Symp. Spread Spectrum Tech. and Appl
, pp. 369-373
-
-
Zhang, J.1
-
10
-
-
0036612082
-
Sampling Signals w. Finite Rate of Innovation
-
M. Vetterli, P. Marziliano, and T. Blu, "Sampling Signals w. Finite Rate of Innovation," IEEE Trans. Signal Proc., vol. 50, pp. 1417-1428, 2002.
-
(2002)
IEEE Trans. Signal Proc
, vol.50
, pp. 1417-1428
-
-
Vetterli, M.1
Marziliano, P.2
Blu, T.3
-
11
-
-
0021822541
-
Computation of the Singular Value Decomposition Using Mesh-Connected Processors
-
R. P. Brent, F. T. Luk, and C. V. Loan, "Computation of the Singular Value Decomposition Using Mesh-Connected Processors," J. VLSI Computer Systems, vol. 1, no. 3, pp. 243-270, 1985.
-
(1985)
J. VLSI Computer Systems
, vol.1
, Issue.3
, pp. 243-270
-
-
Brent, R.P.1
Luk, F.T.2
Loan, C.V.3
-
12
-
-
34547690965
-
A Systolic VLSI Architecture for Complex SVD,
-
Master's thesis, Rice University
-
N. D. Hemkumar, "A Systolic VLSI Architecture for Complex SVD," Master's thesis, Rice University, 1991.
-
(1991)
-
-
Hemkumar, N.D.1
-
14
-
-
58249084461
-
An Approach for Sprecifying the ADC and AGC Requirements for UWB Digital Receivers
-
Y. Vanderperren, G. Leus, and W. Dehaene, "An Approach for Sprecifying the ADC and AGC Requirements for UWB Digital Receivers," in IET Seminar on UWB Syst., Technologies and Applic., 2006.
-
(2006)
IET Seminar on UWB Syst., Technologies and Applic
-
-
Vanderperren, Y.1
Leus, G.2
Dehaene, W.3
-
17
-
-
4143101167
-
DSP System Design using the BEE Hardware Emulation Environment
-
B. Richards, C. Chang, and R. Brodersen, "DSP System Design using the BEE Hardware Emulation Environment," in Proc. 37th Asilomar Conf. Sig., Syst. and Comp., 2003.
-
(2003)
Proc. 37th Asilomar Conf. Sig., Syst. and Comp
-
-
Richards, B.1
Chang, C.2
Brodersen, R.3
-
18
-
-
50249143439
-
-
Xilinx App. Note 059, Gate Count Capacity Metrics for FPGAs.
-
Xilinx App. Note 059, "Gate Count Capacity Metrics for FPGAs."
-
-
-
|