메뉴 건너뛰기




Volumn , Issue , 2007, Pages 828-833

Synchronization for subsampling digital UWB receiver: A holistic approach

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARSENIC; DIGITAL ARITHMETIC; INTEGRATED CIRCUITS; RADIO RECEIVERS; TELECOMMUNICATION SYSTEMS; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 50249164818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICUWB.2007.4381059     Document Type: Conference Paper
Times cited : (1)

References (18)
  • 1
    • 25844521523 scopus 로고    scopus 로고
    • A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling
    • M. Chen and R. Brodersen, "A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling," IEICE Trans. Electronics, vol. E88-C, no. 6, pp. 1114-1121, 2005.
    • (2005) IEICE Trans. Electronics , vol.E88-C , Issue.6 , pp. 1114-1121
    • Chen, M.1    Brodersen, R.2
  • 2
    • 42549086692 scopus 로고    scopus 로고
    • A Flexible Low Power Sub-sampling UWB Receiver Based on Line Spectrum Estimation Methods
    • Y. Vanderperren, W. Dehaene, and G. Leus, "A Flexible Low Power Sub-sampling UWB Receiver Based on Line Spectrum Estimation Methods," in Proc. IEEE Int. Conf. on Comm., 2006.
    • (2006) Proc. IEEE Int. Conf. on Comm
    • Vanderperren, Y.1    Dehaene, W.2    Leus, G.3
  • 3
    • 29044431930 scopus 로고    scopus 로고
    • Timing Acquisition in Ultra-wideband Communication Systems
    • S. Aedudodla, S. Vijayakumaran, and T. Wong, "Timing Acquisition in Ultra-wideband Communication Systems," IEEE Trans. Vehic. Tech., vol. 54, no. 5, pp. 1570-1583, 2005.
    • (2005) IEEE Trans. Vehic. Tech , vol.54 , Issue.5 , pp. 1570-1583
    • Aedudodla, S.1    Vijayakumaran, S.2    Wong, T.3
  • 6
    • 28844506779 scopus 로고    scopus 로고
    • Timing Ultra-Wideband Signals with Dirty Templates
    • L. Yang and G. Giannakis, "Timing Ultra-Wideband Signals with Dirty Templates," IEEE Trans. Comm., vol. 53, no. 11, pp. 1952 - 1963, 2005.
    • (2005) IEEE Trans. Comm , vol.53 , Issue.11 , pp. 1952-1963
    • Yang, L.1    Giannakis, G.2
  • 7
    • 33847356761 scopus 로고    scopus 로고
    • Synchronization of Ultra-Wideband Signals in the Dense Multipath Channel,
    • Ph.D. dissertation, Univ. Southern Calif
    • E. Homier, "Synchronization of Ultra-Wideband Signals in the Dense Multipath Channel," Ph.D. dissertation, Univ. Southern Calif., 2004.
    • (2004)
    • Homier, E.1
  • 8
    • 41649083689 scopus 로고    scopus 로고
    • Low-Complexity Subspace Methods for Channel Estimation and Synchronization in Ultra-Wideband Systems
    • I. Maravić and M. Vetterli, "Low-Complexity Subspace Methods for Channel Estimation and Synchronization in Ultra-Wideband Systems," in Int. Workshop on UWB Systems, 2003.
    • (2003) Int. Workshop on UWB Systems
    • Maravić, I.1    Vetterli, M.2
  • 9
    • 26944436289 scopus 로고    scopus 로고
    • Principal Components Tracking Algorithms for Synchronization and Channel Identification in UWB Systems
    • J. Zhang et al., "Principal Components Tracking Algorithms for Synchronization and Channel Identification in UWB Systems," in IEEE 8th Int. Symp. Spread Spectrum Tech. and Appl., 2004, pp. 369-373.
    • (2004) IEEE 8th Int. Symp. Spread Spectrum Tech. and Appl , pp. 369-373
    • Zhang, J.1
  • 10
    • 0036612082 scopus 로고    scopus 로고
    • Sampling Signals w. Finite Rate of Innovation
    • M. Vetterli, P. Marziliano, and T. Blu, "Sampling Signals w. Finite Rate of Innovation," IEEE Trans. Signal Proc., vol. 50, pp. 1417-1428, 2002.
    • (2002) IEEE Trans. Signal Proc , vol.50 , pp. 1417-1428
    • Vetterli, M.1    Marziliano, P.2    Blu, T.3
  • 11
    • 0021822541 scopus 로고
    • Computation of the Singular Value Decomposition Using Mesh-Connected Processors
    • R. P. Brent, F. T. Luk, and C. V. Loan, "Computation of the Singular Value Decomposition Using Mesh-Connected Processors," J. VLSI Computer Systems, vol. 1, no. 3, pp. 243-270, 1985.
    • (1985) J. VLSI Computer Systems , vol.1 , Issue.3 , pp. 243-270
    • Brent, R.P.1    Luk, F.T.2    Loan, C.V.3
  • 12
    • 34547690965 scopus 로고
    • A Systolic VLSI Architecture for Complex SVD,
    • Master's thesis, Rice University
    • N. D. Hemkumar, "A Systolic VLSI Architecture for Complex SVD," Master's thesis, Rice University, 1991.
    • (1991)
    • Hemkumar, N.D.1
  • 18
    • 50249143439 scopus 로고    scopus 로고
    • Xilinx App. Note 059, Gate Count Capacity Metrics for FPGAs.
    • Xilinx App. Note 059, "Gate Count Capacity Metrics for FPGAs."


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.