Steiner tree construction based on congestion for the global routing problem

Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Volumn , Issue , 2003, Pages 28-31

  Behjat, L ^a   Vanneli, A ^b  

^a UNIVERSITY OF CALGARY   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Channel capacity; Circuits; Design engineering; Integer linear programming; Mathematical model; Mathematical programming; Minimization; Physics computing; Routing; Very large scale integration

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGER PROGRAMMING; MATHEMATICAL MODELS; MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

DESIGN ENGINEERING; INTEGER LINEAR PROGRAMMING; MATHEMATICAL PROGRAMMING MODELS; PHYSICAL DESIGN; PROBLEM FORMULATION; ROUTING; STEINER TREE CONSTRUCTION; WIRELENGTH MINIMIZATION;

CHANNEL CAPACITY;

EID: 50249141934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWSOC.2003.1213000     Document Type: Conference Paper

References (11)

1. C. J. Alpert, M. Hirkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan, and P. Villarrubia. Buffered steiner trees for difficult instances. In In proceedings of International Symposium on Physical Design, pages 4-9, 2001.
2. L. Behjat, D. Kucar, and A. Vannelli. A novel eigenvector technique for large scale combinatorial problems in vlsi layout. Journal of Combinatorial Optimization, 2002.
3. L. Behjat, A. Vannelli, and A. Kennings. Congestion based mathematical programming models for global routing. In In proceedings of Mid-West Symposium on Circuits and Systems, 2002.
4. J. Cong, A. B. Kahng, and K. Leung. Efficient algorithms for minimum shortest path steiner arborescence problem with application to vlsi physical design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(1):24-39, 1998.
5. H. Etawil, S. Areibi, and A. Vannelli. Attractor-repeller approach for global placement. InIEEE Int. Conf. on CAD, 1999.
6. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. An exact algorithm for coupling-free routing. In International Symposium on Physical Design, pages 10-15, 2001.
7. K. Kozminski. Benchmarks for layout synthesis-evaluation and current status. In 28th ACM/IEEE Design Automation Conference, pages 265-270, 1991.
8. P. Raghavan and C. D. Thompson. Randomized rounding: A technique for provably good algorithms and algorithmic proofs. Combinatorica, 7(4):365-374, 1987.
9. N. Sherwani. Algorithms for VLSI physical design automation. Kluwer Academic Publishers, Dorrecht, The Netherlands, 1999.
10. T.Lengauer and M. Lungering. Provably good global routing of integrated circuits. SIAM Journal of Optimization, 11(1):1-30, 2000.
11. R. Vanderbei. LOQO: An interior point code for quadratic programming. Technical report, Princeton University, Princeton, NJ, 1998.