Low power floating point MAFs-a comparative study

6th International Symposium on Signal Processing and Its Applications, ISSPA 2001 - Proceedings; 6 Tutorials in Communications, Image Processing and Signal Analysis

Volumn 1, Issue , 2001, Pages 284-287

  Pillai, R V K ^a   Shah, S Y A ^b   Al Khalili, A J ^b   Al Khalili, D ^c  

^a Agere Systems   (United States)

^b Civil and Environmental Engineering   (Canada)

^c ROYAL MILITARY COLLEGE OF CANADA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING;

COMPARATIVE STUDIES; CRITICAL PATH DELAYS; DATA-PATH ARCHITECTURE; FLOATING POINTS; FUNCTIONAL PARTITIONING; OPERATION CYCLES; POWER REDUCTIONS; SWITCHING ACTIVITIES;

CMOS INTEGRATED CIRCUITS;

EID: 50249141764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSPA.2001.949833     Document Type: Conference Paper

References (12)

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3. Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko and Tadashi Sumi, "Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition", IEEE Journal of Solid State Circuits, Vol. 31, No. 8, pp. 1157-1164, August 1996.
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7. R. V. K. Pillai, D. Al-Khalili and A. J. Al-Khalili, "A Low Power Architecture for Floating Point MAC Fusion", IEE Proceedings-Comp. Digit. Tech, Vol. 147, No. 4, pp. 288-296, July 2000.
8. R. V. K. Pillai, "On Low Power Floating Point DSP Data Path Architectures", Ph. D Thesis-Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, 1999.
9. David J. Kuck, Douglass S. Parker and Ahmed H. Ameh, "Analysis of Rounding Methods in Floating-Point Arithmetic", IEEE Transactions on Computers, Vol. C-26, No. 7, pp. 643-650, July 1977.
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12. S. Y. A. Shah, "On Synthesis and Optimization of Floating Point Units", Master's thesis-Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec, Nov. 2000.