A portable memory access framework on reconfigurable computers

ICFPT 2007 - International Conference on Field Programmable Technology

Volumn , Issue , 2007, Pages 333-336

  Huang, Miaoqing ^a   Gonzalez, Ivan ^a   El Ghazawi, Tarek ^a  

^a The George Washington University

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL MODELING; HARDWARE COSTS; HARDWARE DESIGNS; HARDWARE RESOURCE UTILIZATION; INTERNATIONAL CONFERENCES; LOCAL MEMORIES; MEMORY ACCESSES; PERFORMANCE IMPACTS; RECONFIGURABLE COMPUTERS;

TECHNOLOGY;

COMPUTER HARDWARE;

EID: 50149114304     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2007.4439279     Document Type: Conference Paper

References (5)

1. M. Vuletić, P. Ienne, C. Claus, and W. Stechele, "Multithreaded virtual-memory-enabled reconfigurable hardware accelerators," in Proc. IEEE International Conference on Field Programmable Technology 2006 (FPT 2006), Dec. 2006, pp. 197-204.
2. M. Dales, "Managing a reconfigurable processor in a general purpose workstation environment," in Proc. Design, Automation and Test in Europe Conference and Exhibition, 2003 (DATE'03), Mar. 2003, pp. 980-985.
3. M. Vuletić, L. Pozzi, and P. lenne, "Virtual memory window for application-specific reconfigurable coprocessors," IEEE Trans. VLSI Syst., vol. 14, no. 8, pp. 910-915, Aug. 2006.
4. I. Maalej, G. Gogniat, M. Abid, and J. L. Philippe, "Interface design approach for system on chip based on configuration," in Proc. 2003 International Symposium on Circuits and Systems, vol. 5, May 2003, pp. 593-596.
5. M. Huang, T. El-Ghazawi, B. Larson, and K. Gaj, "Development of block-cipher library for reconfigurable computers," in Proc. IEEE 3rd Southern Conference on Programmable Logic 2007 (SPL'07), Feb. 2007, pp. 191-194.