A dynamically reconfigurable architecture combining pixel-level SIMD and operation-pipeline modes for high frame rate visual processing

ICFPT 2007 - International Conference on Field Programmable Technology

Volumn , Issue , 2007, Pages 321-324

  Iwata, Nao ^a   Kagami, Shingo ^a   Hashimoto, Koichi ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; DATA STORAGE EQUIPMENT; IMAGE CODING; IMAGE PROCESSING; IMAGING SYSTEMS; IMAGING TECHNIQUES; OPTICAL DATA PROCESSING; PIPELINES; TECHNOLOGY; VISUAL COMMUNICATION;

DYNAMICALLY RECONFIGURABLE ARCHITECTURE; HIGH FRAME RATE; IMAGE-PROCESSING ALGORITHMS; INSTRUCTION REGISTER; INTERNATIONAL CONFERENCES; LOCAL MEMORIES; MESH PROCESSING; ON-CHIP MEMORIES; PROPOSED ARCHITECTURES; RECONFIGURABLE PROCESSORS; SIMULATION RESULTS; VISUAL PROCESSING;

PIPELINE PROCESSING SYSTEMS;

EID: 50149103942     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2007.4439276     Document Type: Conference Paper

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