A theoretical framework for on-chip stochastic communication analysis

2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Volumn , Issue , 2006, Pages

  Bogdan, Paul ^a   Marculescu, Radu ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANCE; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; RELIABILITY;

COMMUNICATION ANALYSIS; DESIGN IMPLICATIONS; DESIGN UNCERTAINTY; INTERNATIONAL CONFERENCES; MANUFACTURABILITY; NANO SCALING; NANO-NET; NANO-NETWORKS; ON CHIPS; ON-CHIP COMMUNICATIONS; ON-CHIP MULTIPROCESSOR; SYSTEM LEVELS; VLSI TECHNOLOGIES;

COMMUNICATION;

EID: 50149089115     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANONET.2006.346230     Document Type: Conference Paper

References (13)

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