Designing for low power

Electrical Performance of Electronic Packaging, EPEP

Volumn , Issue , 2006, Pages 3-6

  Rahal Arabi, Tawfik ^a   Muhtaroglu, Ali ^a   Taylor, Greg ^b  

^a Mobile Platform Architecture Development

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; CUSTOMER SATISFACTION; ELECTRIC POWER TRANSMISSION; ELECTRONICS PACKAGING; ENERGY EFFICIENCY; LEAD; MICROPROCESSOR CHIPS;

APPLIED (CO); COMPUTING PLATFORMS; DESIGN APPROACHES; ELECTRICAL PERFORMANCES; ELECTRONIC PACKAGING; ENERGY EFFICIENT; FUNDAMENTAL CHANGES; HIGH PERFORMANCE MICROPROCESSORS; LOW POWERS; MULTI-CORES; PACKAGING LEVELS; POWER DELIVERY; POWER LED; POWER SAVINGS;

ENERGY CONSERVATION;

EID: 50049103801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2006.321176     Document Type: Conference Paper

References (2)

1. Gelsinger, P.P. "Gigascale integration for teraops performance-challenges, opportunities, and new frontiers", 41st Design Automation Conference, 2004 Proceedings.
2. Yeager, H.L.; Patyra, M.J.; Reyes, R.; Bowman, K.A. "Microprocessor power optimization through multi-performance device insertion.", 2004 Symposium on VLSI Circuits. Digest of Technical Papers. 17-19 June 2004 Page(s):334-337