Dynamic reconfiguration: Core relocation via partial bitstreams filtering with minimal overhead

2006 International Symposium on System-on-Chip, SOC

Volumn , Issue , 2006, Pages

  Ferrandi, Fabrizio ^a   Novati, Marco ^a   Morandi, Massimo ^a   Santambrogio, Marco D ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAMS; DYNAMIC RE-CONFIGURATION; HARDWARE FUNCTIONALITIES; INTERNATIONAL SYMPOSIUM; NEW APPROACHES; PARTIAL RECONFIGURATION; RE-CONFIGURABLE COMPUTING; RUN-TIME; SINGLE MODULES; SPACE ALLOCATION; SYSTEM ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COLUMNS (STRUCTURAL); DYNAMIC MODELS; INTEGRATED CIRCUITS; WAVE FILTERS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 50049103264     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSOC.2006.322008     Document Type: Conference Paper

References (9)

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3. S. Kelem. Virtex series configuration architecture user guide. Xilinx XAPP151, 2003.
4. M. Porrmann H. Kalte, G. Lee and U. Rückert. Replica: A bitstrearn manipulation filter for module relocation in partial reconfigurable systems. In The 12th Reconfigurable Architectures Workshop (RAW 2005), 2005.
5. Xilinx Inc. Two flows for partial reconfiguration: Module based or small bit manipulations. XAPP290, May 2002.
6. Edson Horta and John W. Lockwood. Parbit: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (fbgas). Washington University, Department of Computer Science, Technical Report WUCS-01-13, July 2001.
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8. U. Ruckert H. Kalte, M. Porrmann. System-on-programmable-chip approach enabling online fine-grained 1d-placement. In 18th International Parallel and Distributed Processing Symposium (IPDPS'04), 2004.
9. Fabrizio Ferrandi, Marco D. Santambrogio, and Donatella Sciuto. A design methodology for dynamic reconfiguration: The caronte architecture. In The 12th Reconfigurable Architectures Workshop (RAW 2005), 2005.