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Volumn , Issue , 2006, Pages 820-824
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Via interconnections for wafer level packaging: Impact of via shape on spray coating behavior
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Author keywords
[No Author keywords available]
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Indexed keywords
CHIP SCALE PACKAGES;
CLADDING (COATING);
COATINGS;
DIGITAL IMAGE STORAGE;
ELECTRIC CONNECTORS;
ELECTRONIC EQUIPMENT MANUFACTURE;
ETCHING;
GEOMETRICAL OPTICS;
IMAGE SENSORS;
LITHOGRAPHY;
METALLIZING;
NONMETALS;
OPTICAL SENSORS;
PACKAGING;
PAPER COATING;
PESTICIDES;
PLASMA ETCHING;
PLASMA STABILITY;
SENSORS;
SILICON;
SILICON WAFERS;
SPRAYING;
TECHNOLOGY;
ADVANCED PACKAGING;
BOND PADS;
DIRECT CONTACTS;
ELECTRICAL CONNECTIONS;
FORMING PROCESSES;
OPTICAL IMAGING;
PACKAGING TECHNOLOGIES;
PROCESS STEPS;
PRODUCTION CONDITIONS;
REDISTRIBUTION LAYER;
SPRAY COATINGS;
TRANSMISSION PATHS;
WAFER-LEVEL PACKAGING;
ELECTRONICS PACKAGING;
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EID: 50049086860
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/EPTC.2006.342818 Document Type: Conference Paper |
Times cited : (3)
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References (4)
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