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Volumn , Issue , 2006, Pages 820-824

Via interconnections for wafer level packaging: Impact of via shape on spray coating behavior

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CLADDING (COATING); COATINGS; DIGITAL IMAGE STORAGE; ELECTRIC CONNECTORS; ELECTRONIC EQUIPMENT MANUFACTURE; ETCHING; GEOMETRICAL OPTICS; IMAGE SENSORS; LITHOGRAPHY; METALLIZING; NONMETALS; OPTICAL SENSORS; PACKAGING; PAPER COATING; PESTICIDES; PLASMA ETCHING; PLASMA STABILITY; SENSORS; SILICON; SILICON WAFERS; SPRAYING; TECHNOLOGY;

EID: 50049086860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2006.342818     Document Type: Conference Paper
Times cited : (3)

References (4)
  • 2
    • 33847309664 scopus 로고    scopus 로고
    • Novel Wafer Level Package Technology Studies for Image Sensor Devices
    • Singapore
    • G. Viswanadam, F. Bieck and N. Suthiwongsunthorn, Novel Wafer Level Package Technology Studies for Image Sensor Devices. EPTC conference 2005, Singapore.
    • (2005) EPTC conference
    • Viswanadam, G.1    Bieck, F.2    Suthiwongsunthorn, N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.