-
1
-
-
35248857942
-
-
Bardin, S., Finkel, A., Leroux, J., Petrucci, L.: FAST: Fast Acceleration of Symbolic Transition systems. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, 2725, Springer, Heidelberg (2003)
-
Bardin, S., Finkel, A., Leroux, J., Petrucci, L.: FAST: Fast Acceleration of Symbolic Transition systems. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, Springer, Heidelberg (2003)
-
-
-
-
2
-
-
49949093599
-
From Pointer Systems to Counter Systems Using Shape Analysis
-
Bardin, S., Fiukel, A., Lozes, E.: From Pointer Systems to Counter Systems Using Shape Analysis. In: Proc. of AVIS 2006 (2006)
-
(2006)
Proc. of AVIS
-
-
Bardin, S.1
Fiukel, A.2
Lozes, E.3
-
3
-
-
33749842015
-
-
Bouajjani, A., Bozga, M., Habermehl, P., Iosif, R., Moro, P., Vojnar, T.: Programs with Lists are Counter Automata. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, 4144, Springer. Heidelberg (2006)
-
Bouajjani, A., Bozga, M., Habermehl, P., Iosif, R., Moro, P., Vojnar, T.: Programs with Lists are Counter Automata. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, Springer. Heidelberg (2006)
-
-
-
-
4
-
-
4444251518
-
Efficient Verification of Sequential and Concurrent C Programs
-
Chaki, S., Clarke, E., Groce, A., Ouaknine, J., Strichman, O., Yorav, K.: Efficient Verification of Sequential and Concurrent C Programs. Formal Methods in System Design 25(2-3), 129-166 (2004)
-
(2004)
Formal Methods in System Design
, vol.25
, Issue.2-3
, pp. 129-166
-
-
Chaki, S.1
Clarke, E.2
Groce, A.3
Ouaknine, J.4
Strichman, O.5
Yorav, K.6
-
5
-
-
84889358019
-
-
John Wiley and Sons, Inc, Hoboken, New Jersey
-
Chu, P.P.: RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability. John Wiley and Sons, Inc, Hoboken, New Jersey (2006)
-
(2006)
RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability
-
-
Chu, P.P.1
-
6
-
-
84863901157
-
-
Comon, H., Jurski, Y.: Multiple Counters Automata, Safety Analysis and Presburger Arithmetic. In: Vardi, M.Y. (ed.) CAV 1998. LNCS, 1427, Springer. Heidelberg (1998)
-
Comon, H., Jurski, Y.: Multiple Counters Automata, Safety Analysis and Presburger Arithmetic. In: Vardi, M.Y. (ed.) CAV 1998. LNCS, vol. 1427, Springer. Heidelberg (1998)
-
-
-
-
7
-
-
49949091508
-
-
Habermehl, P., Iosif, R., Rogalewicz, A., Vojnar, T.: Proving Termination of Tree Manipulating Programs. Verimag. TR-2007-1 (2007). www-verimag.imag.fr/ index.php?page=techrep-list
-
Habermehl, P., Iosif, R., Rogalewicz, A., Vojnar, T.: Proving Termination of Tree Manipulating Programs. Verimag. TR-2007-1 (2007). www-verimag.imag.fr/ index.php?page=techrep-list
-
-
-
-
8
-
-
35248827669
-
Software Verification with Blast
-
Ball, T, Rajamani, S.K, eds, Model Checking Software, Springer, Heidelberg
-
Henzinger, T.A., Jhala, R., Majumdar, R., Sutre, G.: Software Verification with Blast. In: Ball, T., Rajamani, S.K. (eds.) Model Checking Software. LNCS, vol. 2648, Springer, Heidelberg (2003)
-
(2003)
LNCS
, vol.2648
-
-
Henzinger, T.A.1
Jhala, R.2
Majumdar, R.3
Sutre, G.4
-
9
-
-
33746904347
-
NetFlow Probe Intended for High-Speed Networks
-
IEEE Computer Society, Los Alamitos
-
Kořenek, J., Pečenka, T., Žádník. M.: NetFlow Probe Intended for High-Speed Networks. In: Proc. of FPL 2005. IEEE Computer Society, Los Alamitos (2005)
-
(2005)
Proc. of FPL
-
-
Kořenek, J.1
Pečenka, T.2
Žádník, M.3
-
11
-
-
49949106860
-
-
IEEE Computer Society. IEEE Std 1076-2000. IEEE Standard VHDL Language Reference Manual. IEEE Std 1076-2000. Pages. 290. (2000) ISBN: 0-7381-1948-2
-
IEEE Computer Society. IEEE Std 1076-2000. IEEE Standard VHDL Language Reference Manual. IEEE Std 1076-2000. Pages. 290. (2000) ISBN: 0-7381-1948-2
-
-
-
-
13
-
-
49949091137
-
-
Liberouter Project Home
-
Liberouter Project Homepage. www.liberouter.org
-
-
-
-
15
-
-
49949109983
-
-
Podelski, A., Rybalchenko, A.: ARMC: The Logical Choice for Software Model Checking with Abstraction Refinement. In: Hanus, M. (ed.) PADL 2007. LNCS, 4354, Springer. Heidelberg (2006)
-
Podelski, A., Rybalchenko, A.: ARMC: The Logical Choice for Software Model Checking with Abstraction Refinement. In: Hanus, M. (ed.) PADL 2007. LNCS, vol. 4354, Springer. Heidelberg (2006)
-
-
-
-
16
-
-
49949119928
-
-
Smrčka, A.: VHD2CA. In: A Prototype of a Translator from VHDL to Counter Automata, www.fit.vutbr.cz/~smrcka/projects/vhd2ca/
-
Smrčka, A.: VHD2CA. In: A Prototype of a Translator from VHDL to Counter Automata, www.fit.vutbr.cz/~smrcka/projects/vhd2ca/
-
-
-
-
17
-
-
49949102931
-
Verifying VHDL Design with Multiple Clocks in SMV
-
Brim, L, Haverkort, B, Leucker, M, van de Pol, J, eds, FMICS 2006 and PDMC 2006, Springer, Heidelberg
-
Šafránek, D., Smrčka, A., Vojnar, T., Řehák, V., Řehák, Z., Matoušek, P.: Verifying VHDL Design with Multiple Clocks in SMV. In: Brim, L., Haverkort, B., Leucker, M., van de Pol, J. (eds.) FMICS 2006 and PDMC 2006. LNCS, vol. 4346, Springer, Heidelberg (2007)
-
(2007)
LNCS
, vol.4346
-
-
Šafránek, D.1
Smrčka, A.2
Vojnar, T.3
Řehák, V.4
Řehák, Z.5
Matoušek, P.6
-
18
-
-
26444439000
-
-
Yavuz-Kahveci, T., Bartzis, C., Bultan, T.: Action Language Verifier, Extended. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, 3576, Springer. Heidelberg (2005)
-
Yavuz-Kahveci, T., Bartzis, C., Bultan, T.: Action Language Verifier, Extended. In: Etessami, K., Rajamani, S.K. (eds.) CAV 2005. LNCS, vol. 3576, Springer. Heidelberg (2005)
-
-
-
|