Dynamic co-processor architecture for software acceleration on CSoCs

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 127-133

  Mitra, Abhishek ^a   Guo, Zhi ^a   Banerjee, Anirban ^a   Najjar, Walid ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET PROTOCOLS; SOFTWARE ARCHITECTURE;

CO-PROCESSOR ARCHITECTURE; COMPUTER DESIGNS; CONFIGURABLE SYSTEMS; CPU CORES; EXECUTION MODELS; INTERNATIONAL CONFERENCES; IP CORES; NEW DESIGN; NEW GENERATION; PARTIAL RECONFIGURATION; RE-CONFIGURABLE; SOFTWARE ACCELERATION; SOFTWARE TOOLS; SOURCE CODING; SYSTEM DESIGNERS;

COMPUTER SOFTWARE;

EID: 49749118811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380805     Document Type: Conference Paper

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