Predictive delay evaluation on emerging CMOS technologies: A simulation framework

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 492-497

  Sellier, Manuel ^a   Portal, Jean Michel ^b   Borot, Bertrand ^a   Colquhoun, Steve ^a   Ferrant, Richard ^a   Bœeuf, Frédéric ^a   Farcy, Alexis ^a  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRONICS ENGINEERING; NONMETALS; SILICON; TECHNOLOGY;

BUFFER INSERTION; CMOS TECHNOLOGIES; ELECTRICAL CIRCUITS; ELECTRONIC DESIGNS; FUTURE TECHNOLOGIES; INTERCONNECT LINES; INTERNATIONAL SYMPOSIUM; PREDICTIVE MODELING; PREDICTIVE SIMULATIONS; SIMULATION FRAMEWORK; SIMULATION RESULTS; SPICE-MODELS; WIRE DELAYS;

SPICE;

EID: 49749085586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479784     Document Type: Conference Paper

References (9)

1. ITRS Roadmap Process Integration Devices and Structures 2005 edition, available http://www.itrs.net/Links/2005ITRS/PIDS2005.pdf
2. T. Skotnicki et al, "The Voltage-Doping Transformation : A New Approach to the Modeling of MOSFET Short-Channel Effects", Elec. Dev. Lett., Vol 9, No. 3, 1988 [3] Ref Alexis wire delay
3. A. Farcy, M. Gallitre, V. Arnal, M. Sellier, L. Guibe, B. Blampey, C. Bermond, B. Fléchet, J. Torres, "Impact of process parameters on circuit performance for the 32 nm technology node", in Proc. of the Conference on Materials for Advanced Metallization (MAM) , 2007
4. ITRS Roadmap Interconnect 2005 edition, available http://www.itrs.net/ Links/2005ITRS/Interconnect2005.pdf
5. Seong-Dong Kim, Cheol-Min Park , J.C.S. Woo "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. II. Quantitative analysis" IEEE Trans. Elec. Dev, vol. 49, pp457-472, March 2002.
6. F. Boeuf, M. Sellier, F. Payet, B. Borot and T. Skotnicki, "Using MASTAR as a Pre-SPICE Model Generator for Early Technology Assessment and Circuit", Simulation submitted to Japanese Journal of Applied Physics.
7. M. Sellier, B. Borot, J.M. Portal and F. Boeuf ,"A Universal Predictive Model for Circuit Performance Assessment", Proc. of the 6th Symposium SiO2 Advanced Dielectrics and Related Devices, (Palermo), pp. 182-183, 2006.
8. F. Charlet, C. Bermond, S. Putot, G. Le Carval, B. Flechet, "Extraction of (R,L,C,G) interconnect parameters in 2D transmission lines using fast and efficient numerical tools", Proc. of SISPAD, Seattle, 2000.
9. W.F.A. Besling, V. Arnal, J.F. Guillaumond, C. Guedj, M. Broekaart, L.L. Chapelon, A. Farcy, L. Arnaud, and J. Torres, in Proc. of the IEDM conference, p. 325, 2004.