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Proceedings ISM Workshops 2007 9th IEEE International Symposium on Multimedia - Workshops

Volumn , Issue , 2007, Pages 401-406

Bandwidth-efficient encoder framework for H.264/AVC scalable extension

(4) Chen, Yi Hau a Chuang, Tzu Der a Chen, Yu Jen a Chen, Liang Gee a

a NATIONAL TAIWAN UNIVERSITY (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC NETWORK TOPOLOGY; IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS; PROGRAMMING THEORY; STANDARDS; SULFATE MINERALS; TECHNICAL PRESENTATIONS; TELECOMMUNICATION SYSTEMS; VISUAL COMMUNICATION;

B-FRAME; CODING TOOLS; FINE GRANULARITY SCALABILITY; H.264/AVC; HARDWARE DESIGNS; HETEROGENEOUS NETWORKS; HIGH-DEFINITION; INTERNATIONAL SYMPOSIUM; MEMORY BANDWIDTHS; QUALITY DEGRADATION; SCALABLE VIDEO CODING; STREAMING APPLICATIONS; VIDEO CODING STANDARDS;

ADAPTIVE ALGORITHMS;

EID: 49649100468 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISMW.2007.4476002 Document Type: Conference Paper

Times cited : (7)

References (7)

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- (2006)

2
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- JTC1, "Joint Scalable Video Model 8.0," ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6, Doc
- ISO/IEC JVT-U202, Oct
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- (2006)

3
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- Analysis of hierarchical B pictures and MCTF
- Heiko Schwarz, Detlev Marpe, and Thomas Wiegand, "Analysis of hierarchical B pictures and MCTF," in Proc. IEEE International Conference on Multimedia and Expo, 2006, pp. 1929-1932.
- (2006) Proc. IEEE International Conference on Multimedia and Expo , pp. 1929-1932
- Schwarz, H.¹ Marpe, D.² Wiegand, T.³

4
- 33646424425
- Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering
- C.-T. Huang, C.-Y. Chen, Y.-H. Chen, and L.-G. Chen, "Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.
- (2005) Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing
- Huang, C.-T.¹ Chen, C.-Y.² Chen, Y.-H.³ Chen, L.-G.⁴

5
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- System analysis of VLSI architecture for motion-compensated temporal filtering
- C.-Y. Chen, C.-T. Huang, Y.-H. Chen, C.-J. Lian, and L.-G. Chen, "System analysis of VLSI architecture for motion-compensated temporal filtering," in Proc. IEEE International Conference on Image Processing, 2005.
- (2005) Proc. IEEE International Conference on Image Processing
- Chen, C.-Y.¹ Huang, C.-T.² Chen, Y.-H.³ Lian, C.-J.⁴ Chen, L.-G.⁵

6
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- On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
- Jan
- J.-C. Tuan, T.-S. Chang, and C.-W. Jen, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Trans. CSVT, vol. 12, no. 1, pp. 61-72, Jan. 2002.
- (2002) IEEE Trans. CSVT , vol.12 , Issue.1 , pp. 61-72
- Tuan, J.-C.¹ Chang, T.-S.² Jen, C.-W.³

7
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- A 1.3tops H.264/AVC single-chip encoder for HDTV applications
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- (2005) Proc. of IEEE ISSCC , pp. 128-588
- Huang, Y.-W.¹ and et, al.²

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