A scalable 2.4-to-2.7GHz Wi-Fi/WiMAX discrete-time receiver in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 362-364

  Montaudon, Franck ^a   Mina, Rayan ^a   Tual, Stephane Le ^a   Joet, Loïc ^a   Saias, Daniel ^a   Hossain, Razak ^a   Sibille, Florent ^a   Corre, Christian ^a   Carrat, Valérie ^a   Chataigner, Emmanuel ^a   Lajoinie, Jérôme ^a   Dedieu, Sébastien ^a   Paillardet, Frédéric ^a   Perea, Ernesto ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; WIRELESS LOCAL AREA NETWORKS (WLAN);

65NM CMOS; DISCRETE TIME; GAIN STAGES; IEEE 802.16E; SAR ADC; SC STRUCTURES; WIFI/WIMAX;

IEEE STANDARDS;

EID: 49549101123     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523207     Document Type: Conference Paper

References (6)

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2. R. Bagheri, A. Mirzaei, S. Chehrazi et al., "An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 480-481, Feb. 2006.
3. S. Karvonen, T. A. D. Riley and J. Kostamovaara, "A CMOS Quadrature Charge-Domain Sampling Circuit with 66-dB SFDR up to 100 MHz," IEEE Trans. Circuits and Systems I, vol. 52, no. 2, pp. 292-304, Feb. 2005.
4. L. Joet, A. Dezzani, F. Montaudon et al., "Advanced 'Fs/2' Discrete-Time GSM Receiver in 90-nm CMOS," Proc. ASSCC, pp. 371-374, Nov. 2006.
5. M. Simon, P. Laaser, V. Filimon et al., "A 802.11a/b/g RF Transceiver in an SoC," ISSCC Dig. Tech. Papers, pp. 562-563, Feb. 2007.
6. D.-R. Huang, S.-W. Kao and Y.-H. Pang, "A WiMAX Receiver with Variable Bandwidth of 2.5-20 MHz and 93 dB Dynamic Gain Range in 0.13-μm CMOS Process," IEEE RFIC Symp., pp. 369-372, Jun. 2007.