A symbolic approach for mixed-signal model checking

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2008, Pages 404-409

  Jesser, Alexander ^a   Hedrich, Lars ^a  

^a GOETHE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY DECISION DIAGRAMS; COMPUTER AIDED DESIGN; DATA STRUCTURES; DIGITAL INTEGRATED CIRCUITS; FILE ORGANIZATION; INDUSTRIAL ENGINEERING; PHASE LOCKED LOOPS;

ANALOG DESIGNS; DESIGN AUTOMATION CONFERENCE; DIGITAL DOMAINS; FORMAL VERIFICATIONS; MIXED SIGNALS; MIXED-SIGNAL CIRCUITS; MULTI-TERMINAL BINARY DECISION DIAGRAMS; PHASE-LOCKED LOOP; SOUTH PACIFIC; SYMBOLIC MODEL CHECKERS; TIMING INFORMATION;

MODEL CHECKING;

EID: 49549101061     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2008.4483984     Document Type: Conference Paper

References (7)

1. T. A. Henzinger, P.-H. Ho, and H. Wong-Toi, "HYTECH: A Model Checker for Hybrid Systems," International Journal on Software Tools for Technology Transfer, vol. 1, no. 1-2, pp. 110-122, 1997.
2. E. Asarin, T. Dang, and O. Maler, "d/dt: A Tool For Reachability Analysis Of Continuous And Hybrid Systems," in 5th IFAC Symposium Nonlinear Control Systems (NOLCOS'01), July 2001.
3. G. Frehse, "PHAVer: Algorithmic Verification of Hybrid Systems Past HyTech," Lecture Notes in Computer Science, vol. 3414, pp. 258-273, February 2005.
4. E. M. Clarke, O. Grumberg, and D. A. Peled, Model Checking. MIT Press, Cambridge, Massachusetts, London, 1999.
5. D. Grabowski, D. Platte, L. Hedrich, and E. Barke, "Time Constrained Verification of Analog Circuits using Model-Checking Algorithms," in Proceedings of the First Workshop on Formal Verification of Analog Circuits (FAC'05), ser. 3, vol. 153, April 2005, pp. 37-52.
6. E. M. Clarke, M. Fujita, P. C. McGeer, K. McMillan, J. C.-Y. Yang, and X. Zhao, "Multi Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation," in International Workshop on Logic Synthesis (IWLS'93), May 1993.
7. W. Hartong, L. Hedrich, and E. Barke, "Model Checking Algorithms for Analog Verification," in Proceedings of the 39th Conference on Design Automation (DAC'02), June 2002, pp. 542-547.