Impact of production control and system factors in semiconductor wafer fabrication

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 3, 2008, Pages 376-389

  Qi, Chao ^b   Sivakumar, Appa Iyer ^b   Gershwin, Stanley B ^a,c  

^a IEEE

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c Massachusetts Institute of Technology   (United States)

Author keywords

Batching; Dispatching; Job release control; Semi conductor wafer fab; Simulation; WIPLOAD control

Indexed keywords

DESIGN OF EXPERIMENTS; DISPERSIONS; ELECTRIC CONDUCTIVITY; ELECTRONICS INDUSTRY; INDUSTRIAL ENGINEERING; INDUSTRIAL MANAGEMENT; MACHINE DESIGN; MICROELECTRONICS; OPTICAL DESIGN; PROCESS CONTROL; PRODUCTION CONTROL; PRODUCTION ENGINEERING; SEMICONDUCTOR MATERIALS; STANDARDS;

BATCHING; CHARTERED SEMICONDUCTOR MANUFACTURING LTD; CYCLE TIME; DISPATCHING; DISPATCHING RULES; ENVIRONMENTAL CONDITIONING; FAB PERFORMANCE; FULL FACTORIAL DESIGN; HIGH OUTPUT; JOB RELEASE CONTROL; ON-WAFER; PERFORMANCE MEASURE; PERFORMANCE MEASURES; RELATIVE IMPACT; RELEASE CONTROL; SEMI-CONDUCTOR WAFER FAB; SEMICONDUCTOR WAFER FABRICATION; SIMULATION; STANDARD DEVIATION; WAFER FAB; WIP INVENTORY; WIPLOAD CONTROL;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 49249084274     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2008.2001214     Document Type: Conference Paper

References (32)

1. J. Fowler and J. Robinson, 1995, Measurement and Improvement of Manufacturing Capacity (MIMAC) Designed Experiment Report Technology Transfer 95062860A-TR, SEMATECH, 1995.
2. J. Fowler, G. L. Hogg, and S. J. Mason, "Workload control in the semiconductor industry," Prod. Plan. Control, vol. 13, no. 7, pp. 568-578, 2002.
3. R. Uzsoy, C. Y. Lee, and L. A. Martin-Vega, "A review of production planning and scheduling models in the semiconductor industry part I: System characteristics, performance evaluation and production planning," IIE Trans., vol. 24, no. 4, pp. 47-60, 1992.
4. G. L. Ragatz and V. A. Mabert, "An evaluation of order review release mechanisms in a job-shop environment," Decis. Sci., vol. 19, pp. 167-189, 1988.
5. P. M. Bobrowski and P. S. Park, "Work release strategies in a dual resource constrained job shop," OMEGA Int. J. Manage. Sci., vol. 17, no. 2, pp. 177-188, 1989.
6. S. A. Melnyk and G. L. Ragatz, "Order review/release: Research issues and perspectives," Int. J. Prod. Res., vol. 27, no. 7, pp. 1081-1096, 1989.
7. L. W. Wein, "Scheduling semiconductor wafer fabrication," IEEE Trans. Semicond. Manuf., vol. 1, no. 3, pp. 115-130, Aug. 1988.
8. C. R. Glassey and M. G. C. Resende, "Closed-loop job release control for VLSI circuit manufacturing," IEEE Trans. Semicond. Manuf., vol. 1, no. 1, pp. 36-46, Feb. 1988.
9. K. R. Baker, "Sequencing rales and due-date assignment in a job shop," Manage. Sci., vol. 30, pp. 1093-1104, 1984.
10. J. Browne and B. J. Davies, "The phased release of batches into a job shop," Int. J. Prod. Manage., vol. 4, pp. 16-27, 1984.
11. S. Shimoyashiro, K. Isoda, and H. Awane, "Input scheduling and load balance control for a job shop," Int. J. Prod Res., vol. 22, pp. 597-605, 1984.
12. J. D. Wisner, "A review of the order release policy research," Int. J. Oper. Prod. Manage., vol. 15, no. 6, pp. 25-40, 1995.
13. D. Bergamaschi, R. Cigolini, M. Perona, and A. Portioli, "Order review and release strategies in a job shop environment: A review and a classification," Int. J. Prod. Res., vol. 35, no. 2, pp. 399-420, 1997.
14. R. Uzsoy, C. Y. Lee, and L. A. Martin-Vega, "A review of production planning and scheduling models in the semiconductor industry part II: Shop-floor control," IIE Trans., vol. 26, no. 5, pp. 44-55, 1994.
15. W. J. Hopp and M. L. Spearman, Factory Physics: Foundations of Manufacturing Management. Singapore: Irwin/McGraw-Hill, 2000.
16. M. L. Spearman, D. L. Woodruff, and W. J. Hopp, "CONWIP: A pull alternative to Kanban," Int. J. Prod. Res., vol. 28, no. 5, pp. 879-894, 1990.
17. M. L. Spearman and M. A. Zazanis, "Push and pull production systems: Issues and comparisons," Oper. Res., vol. 40, no. 3, pp. 521-532, 1992.
18. J. P. Ignizio, "The implementation of CONWIP in semiconductor fabrication facilities," Future Fab, vol. 14, 2003.
19. L. M. Roderick, D. T. Phillips, and G. L. Hogg, "A comparison of order release strategies in production control systems," Int. J. Prod. Res., vol. 30, no. 3, pp. 611-626, 1992.
20. L. F. Atherton and R. W. Atherton, Wafer Fabrication: Factory Performance and Analysis. Norwell, MA: Kluwer Academic, 1995.
21. C. Qi, "Closed-Loop Job Release Based on WIPLOAD Control in Semiconductor Wafer Fabrication," Ph.D. dissertation, Nanyang Technol. Univ., Singapore, 2006.
22. C. Qi, A. I. Sivakumar, and V. K. Ganesan, "Markov process modeling of a system under WIPLOAD control," presented at the Singapore-MIT Alliance (SMA) Annu. Symp. 2005, Singapore, Jan. 2005, unpublished.
23. C. Qi, A. I. Sivakumar, and V. K. Ganesan, "Dynamic job release using proportional control," in Proc. the 33rd Int. Conf. Comput. Ind. Eng., Korea, Mar. 2004.
24. C. Qi and A. I. Sivakumar, "Job release based on WIPLOAD control in semiconductor wafer fabrication," in Proc. 2006 Electron. Pack. Tech. Conf., Singapore, 2006, pp. 665-670.
25. C. Qi, A. I. Sivakumar, and S. G. Gershwin, "An efficient new job release control methodology," in Int. J. Prod. Res., 2008.
26. C. Qi, A. I. Sivakumar, and S. B. Gershwin, "Simulation experimental investigation on job release control in semiconductor wafer fabrication," in Proc. 2007 Winter Simulation Conf., Washington, DC, Dec. 2007.
27. P. R. Philipoom, M. K. Malhotra, and J. B. Jensen, "An evaluation of capacity sensitive order review and release procedures in job shops," Decis. Sci., vol. 24, no. 6, pp. 1109-1133, 1993.
28. P. K. Johri, "Practical issues in scheduling and dispatching in semiconductor wafer fabrication," J. Manuf. Syst., vol. 12, no. 6, pp. 474-485, 1993.
29. A. M. Law and W. D. Kelton, Simulation Modeling and Analysis, 3rd ed. New York: McGraw-Hill, 2000.
30. A. I. Sivakumar, "Simulation based cause and effect analysis of cycle time distribution in semiconductor backend," in Proc 2000 Winter Simulation Conf., Dec. 2000, pp. 1464-1471.
31. P. D. Welch, The Computer Performance Modeling Handbook. New York: Academic, 1983.
32. G. Keppel and T. Wickens, Design and Analysis: A Researcher's Handbook, 4th ed. Upper Saddle River, NJ: Pearson Prentice Hall, 2004.