In-situ surface passivation and metal-gate/high-k dielectric stack formation for N-channel gallium arsenide metal-oxide-semiconductor field-effect transistors

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2008, Pages 26-27

  Chin, Hock Chun ^a   Zhu, Ming ^a   Whang, Sung Jin ^a   Tung, Chih Hang ^b   Samudra, Ganesh S ^a   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ARSENIC COMPOUNDS; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; GALLIUM COMPOUNDS; GATE DIELECTRICS; GATES (TRANSISTOR); ION BEAM ASSISTED DEPOSITION; METALS; MOSFET DEVICES; ORGANIC CHEMICALS; ORGANIC COMPOUNDS; PASSIVATION; SECURITY SYSTEMS; SEMICONDUCTING GALLIUM; SEMICONDUCTING INDIUM; TECHNOLOGY; TRANSISTORS;

DIELECTRIC STACKS; GALLIUM ARSENIDE; IN-SITU; INTERNATIONAL SYMPOSIUM; METAL-ORGANIC CHEMICAL VAPOR DEPOSITION; METAL-OXIDE SEMICONDUCTORS; N -CHANNEL; SURFACE PASSIVATION; VACUUM ANNEALING; VLSI TECHNOLOGIES;

METALLORGANIC CHEMICAL VAPOR DEPOSITION;

EID: 49049104575     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2008.4530782     Document Type: Conference Paper

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