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Volumn , Issue , 2007, Pages 338-341
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Underfill selection strategy for low k, high lead/lead-free flip chip application
a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
BRAZING;
DELAMINATION;
DIELECTRIC MATERIALS;
ELECTRONIC EQUIPMENT MANUFACTURE;
ERROR ANALYSIS;
FLIP CHIP DEVICES;
MECHANICAL PROPERTIES;
MICROSYSTEMS;
NONMETALS;
PACKAGING MATERIALS;
SILICON;
STRESSES;
TECHNOLOGY;
WELDING;
WIRELESS TELECOMMUNICATION SYSTEMS;
APPLICATIONS.;
DIE STRESS;
DIELECTRIC LAYERS;
FLIP CHIPPING;
FLIP-CHIP PACKAGING;
HIGH PROBABILITY;
LOW-K DIELECTRICS;
PACKAGING PROCESSES;
PROPERTY TESTING;
QUALIFICATION TESTING;
RELIABILITY REQUIREMENTS;
RELIABILITY TESTING;
SELECTION PROCESSES;
SELECTION STRATEGIES;
SILICON TECHNOLOGIES;
SOLDER JOINTS;
UNDERFILL;
UNDERFILL MATERIALS;
UNDERFILLS;
CHIP SCALE PACKAGES;
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EID: 48649083547
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IMPACT.2007.4433631 Document Type: Conference Paper |
Times cited : (6)
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References (5)
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