Application-aware power management

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006

Volumn , Issue , 2006, Pages 39-48

  Rajamani, Karthick ^a   Hanson, Heather ^a,b   Rubio, Juan ^a   Ghiasi, Soraya ^a   Rawson, Freeman ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS MONITORING; PENTIUM M; PERFORMANCE MODELS; POWER CONSTRAINTS; POWER MANAGEMENTS; STATE CONTROLS; WORKLOAD CHARACTERISTICS;

APPLICATIONS; ENERGY MANAGEMENT;

ELECTRIC POWER MEASUREMENT;

EID: 48449103420     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2006.302728     Document Type: Conference Paper

References (21)

1. C. Lichtenau, M. Recktenwald, T. Pflueger, R. Hilgendorf, and P. A. Sandon, "PowerTune: An Energy-Efficient High Performance Multi-Processor PowerPC System Architecture," in ACEED, 2003.
2. Advanced Micro Devices, "PowerNow with Optimized Power Management," http://www.amd.com/us-en/0,3715_12353,00.html, Jan. 2006.
3. D. Bodas, "New Server Power-Management Technologies Address Power and Cooling Challenges," Intel Magazine, Sept. 2003.
4. Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd., and Toshiba Corporation, "Advanced Configuration and Power Interface Specification (ACPI) Revision 2.0b." http://www.acpi.info/DOWNLOADS/ACPIspec-2-0b.pdf, Oct. 2002.
5. Intel Corp, "Enhanced Intel SpeedStep technology." http://support.intel.com/support/processors/mobile/pm/sb/CS-007981.htm, Jan. 2006.
6. C. Poirier, R. McGowen, C. Bostak, and S. Naffzigr, "Power and Temperature Control on a 90nm Itanium-Family Processor," in IEEE International Solid-States Circuits Conference 2005, March-April 2005.
7. W. Felter, K. Rajamani, C. Rusu, and T. Keller, "A Performance-Conserving Approach for Reducing Peak Power Consumption in Server Systems," in Proceedings of the 19th ACM International Conference on Supercomputing, June 2005.
8. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget," in Proceedings of the 39th International Symposium on Microarchitecture (MICRO-39), December 2006.
9. R. Kotla, S. Ghiasi, T. W. Keller, and F. L. Rawson, "Scheduling Processor Voltage and Frequency in Server and Cluster Systems," in Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), April 2005.
10. K. Flautner and T. Mudge, "Vertigo: Automatic Performance-Setting for Linux," in Proceedings of the Fifth Symposium on Operating Systems Design and Implementation (OSDI), pp. 105-116, December 2002.
11. J. R. Lorch and A. J. Smith, "Operating System Modifications for Task-Based Speed and Voltage Scheduling," in Proceedings of MobiSys 2003, 2003.
12. B. Lee and D. Brooks, "Statistically Rigorous Regression Modeling for the Microprocessor Design Space," in ISCA-33: Workshop on Modeling, Benchmarking, and Simulation, June 2006.
13. F. Bellosa, "The Benefits of Event-Driven Energy Accounting in Power-Sensitive Systems," in ACM SIGOPS European Workshop, October 2000.
14. A. Weissel and F. Bellosa, "Process Cruise Control: Event-Driven Clock Scaling for Dynamic Power Management," in Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2002), pp. 238-246, October 2002.
15. G. Contreras and M. Martonosi, "Power Prediction of Intel Xscale Processors Using Performance Monitoring Unit Events," in 2005 International Symposium on Low Power Electronics and Design, August 2005.
16. C. Isci, G. Contreras, and M. Martonosi, "Hardware Performance Counters for Detailed Runtime Power and Thermal Estimations," in Hardware Performance Monitor Design and Functionality Workshop in conjunction with 11th International Symposium on High-Performance Computer Architecture (HPCA-11), February 2005.
17. W. L. Bircher, M. Valluri, J. Law, and L. K. John, "Runtime Identification of Microprocessor Energy Saving Opportunitites," in International Symposium on Low Power Electronics and Design (ISLPED), August 2005.
18. Q. Wu, V. Reddi, J. Lee, D. Connors, D. Brooks, M. Martonosi, and D. W. Clark, "A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance," in Proceedings of the 38th International Symposium on Microarchitecture (MICRO-38), November 2005.
19. A. Petitet, C. Whaley, J. Dongarra, and A. Cleary, "HPL - A Portable Implementation of the High-Performance Linpack Benchmark for Distributed-Memory Computers," tech. rep., University of Tennessee, Jan. 20 2004.
20. K. Rajamani, H. Hanson, J. Rubio, S. Ghiasi, and F. Rawson, "Online Power and Performance Estimation for Dynamic Power Management," Tech. Rep. RC24007, IBM Research, July 2006.
21. Radisys Corporation, "Endura LS855 Product Data Sheet." http://www.radisys.com/oem_products/ds-page.cfm?productdatasheetsid=1158, Oct. 10 2004.