Novel fabrication process to realize ultra-thin (EOT = 0.7 nm) and ultra-low-leakage SiON gate dielectrics

13th IEEE International Conference on Advanced Thermal Processing of Semiconductors, RTP 2005

Volumn , Issue , 2005, Pages 23-30

  Matsushita, Daisuke ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC PHYSICS; ATOMS; COORDINATION REACTIONS; CRYSTAL ATOMIC STRUCTURE; CRYSTALS; ELECTRIC CONDUCTIVITY; GATE DIELECTRICS; GATES (TRANSISTOR); INTERNET PROTOCOLS; OXIDE FILMS; RAPID THERMAL ANNEALING; SEMICONDUCTOR MATERIALS; SILICON; SILICON COMPOUNDS; SILICON NITRIDE;

EQUIVALENT OXIDE THICKNESSES; FIRST-PRINCIPLES CALCULATIONS; INCORPORATION RATES; INTERFACIAL PROPERTIES; NITROGEN ATOMS; NOVEL FABRICATION PROCESSES; NOVEL PROCESSES; REACTION MECHANISMS; SION GATE DIELECTRICS; SURFACE LAYERS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 48349096507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2005.1613680     Document Type: Conference Paper

References (11)

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