A Variable Grain Logic Cell architecture for reconfigurable logic cores

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 550-553

  Amagasaki, Motoki ^a   Yamaguchi, Ryoichi ^a   Matsuyama, Kazunori ^a   Iida, Masahiro ^a   Sueyoshi, Toshinori ^a  

^a KUMAMOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATIONS; BENCHMARKING; DELAY CIRCUITS; LOGIC CIRCUITS; LOGIC DEVICES;

BASIC LOGICS; BENCHMARK CIRCUITS; CELL ARCHITECTURES; CONFIGURATION MEMORIES; CRITICAL PATH DELAYS; KEY FEATURES; OPERATION SPEEDS; RECONFIGURABLE; RECONFIGURABLE LOGICS; RIPPLE CARRY ADDERS; TECHNOLOGY MAPPINGS;

CARRY LOGIC;

EID: 48149110487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380714     Document Type: Conference Paper

References (7)

1. M. Amagasaki, T. Shimokawa, K. Matsuyama, R. Yamaguchi, H. Nakayama, M. Iida, T. Sueyoshi, "Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device," In Proc. VLSI-SoC2006, Vol. 2, pp. 198-203, Oct. 2006.
2. J. Cong, S. Xu, "Delay-Oriented Technology Mapping for Heterogeneous FPGAs with Bounded Resources," Proc. ACM/IEEE International Conference on Computer Aided Design, pp. 40-45, Nov. 1998.
3. UCLA CAD-LAB, http://cadlab.cs.ucla.edu/.
4. Xilinx, Inc., Xilinx XC4000 Data Sheet, 1999.
5. J. Cong, Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table based FPGA Designs," Trans, on CAD, Vol. 13, No. 1, pp. 1-12, Jan. 1994.
6. Opencores org, http://www.opencores.org/.
7. K. McElvain, "IWLS'93 Benchmark Set: Version 4.0," Distributed as part of the MCNC International Workshop on Logic Synthesis '93 benchmark distribution, May 1993.