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Volumn 6, Issue , 2007, Pages 4597-4601

New time to digital converter, signal processing, data acquisition, calibration and test hardware for RatCAP

Author keywords

[No Author keywords available]

Indexed keywords

ALTERA STRATIX; AT SYSTEMS; BINARY COUNTERS; CHANNEL TIME; CLOCK PHASES; CLOCK SPEEDS; CONTROL ELECTRONICS; CUSTOM DESIGNED; DAQ SYSTEMS; FIELD PROGRAMMABLE GATE ARRAY; FRONT-END ELECTRONICS; LOGIC CELLS; NUCLEAR SCIENCES; PROPAGATION DELAYS; RAT CONSCIOUS ANIMAL PET; SERIAL DECODER; STATIC RANDOM ACCESS MEMORY; TEST RESULTS; TIME-TO-DIGITAL CONVERTERS; TIMING PERFORMANCE; TOOL SETS; TWO STAGES;

EID: 48149096025     PISSN: 10957863     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NSSMIC.2007.4437132     Document Type: Conference Paper
Times cited : (6)

References (12)
  • 1
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    • RatCAP: Miniaturized head-mounted PET for conscious rodent brain imaging
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    • Vaska, P. et. al.; "RatCAP: miniaturized head-mounted PET for conscious rodent brain imaging", IEEE Trans. Nucl. Sci. vol. 51, no. 5, pp.2718-2722, Oct. 2004
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    • Vaska, P.1    et., al.2
  • 3
    • 4444229513 scopus 로고    scopus 로고
    • Front-end electronics for the RatCAP mobile animal PET scanner
    • J.-F. Pratte, et. al.; "Front-end electronics for the RatCAP mobile animal PET scanner", IEEE Trans. Nucl. Sci., vol. 51, pp. 1318-1323, 2004
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    • Pratte, J.-F.1    et., al.2
  • 4
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    • Design and performance of 0.18 μm CMOS charge preamplifier for APD-based PET scanners
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    • (2004) IEEE Trans. Nucl. Sci , vol.51 , Issue.5
    • Pratte, J.-F.1    et., al.2
  • 5
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    • Front-end electronics for the RatCAP mobile animal PET scanner : Timing discriminator and 32 line address priority serial encoder
    • Portland, USA
    • J.-F. Pratte. et. al. "Front-end electronics for the RatCAP mobile animal PET scanner : Timing discriminator and 32 line address priority serial encoder", Conference Record of the 2003 IEEE NSS/MIC, Portland, USA
    • Conference Record of the 2003 IEEE NSS/MIC
    • Pratte, J.-F.1    et., al.2
  • 6
    • 11844296685 scopus 로고    scopus 로고
    • Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field- programmable Gate Array (FPGA)
    • Oct
    • Jinyuan Wu. et. al. "Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field- programmable Gate Array (FPGA)", IEEE Nucl. Sci, vol 1, 19-25 pp:177-181, Oct. 2003.
    • (2003) IEEE Nucl. Sci , vol.1 , Issue.19-25 , pp. 177-181
    • Jinyuan, W.1    et., al.2
  • 7
    • 0031078640 scopus 로고    scopus 로고
    • Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution
    • Feb
    • J. Kalisz, et. al.; "Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution", IEEE Trans. Inst. and Meas., vol. 46, pp. 51-55, Feb. 1997.
    • (1997) IEEE Trans. Inst. and Meas , vol.46 , pp. 51-55
    • Kalisz, J.1    et., al.2
  • 9
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    • A fast variable transition time pulse generating circuit
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    • Uwe A. Uhmeyer and Jonathan C. Libby "A fast variable transition time pulse generating circuit", 9th IEEE Inst. and Meas. Tech. Conf, pp:152-157, 12-14 May 1992
    • (1992) 9th IEEE Inst. and Meas. Tech. Conf , pp. 152-157
    • Uhmeyer, U.A.1    Libby, J.C.2
  • 10
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    • The Data Acquisition System of the RatCAP Conscious Small Animal PET Tomograph
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    • M. Purschke. et al. "The Data Acquisition System of the RatCAP Conscious Small Animal PET Tomograph", Proc. NSS-MIC, Puerto Rico, 2005.
    • (2005) Proc. NSS-MIC
    • Purschke, M.1
  • 11
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    • Millogic VME Core: VMEbus Slave Core Component User Guide Version 2.0, December 2002. www.millogic.com
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.