Ring prediction for non-uniform cache architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2007, Pages 401-

  Akioka, Sayaka ^a   Li, Feihui ^a   Kandemir, Mahmut ^a   Raghavan, Padma ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPILATION TECHNIQUES; DATA PLACEMENT; DATA REPLACEMENT; INTERNATIONAL CONFERENCES; MEMORY CAPACITIES; NON-UNIFORM CACHE ARCHITECTURE; NON-UNIFORM CACHE ARCHITECTURES; PARALLEL ARCHITECTURES; PREDICTION SCHEMES; WIRE DELAYS;

BUFFER STORAGE; PARALLEL PROCESSING SYSTEMS; TURBO CODES;

FORECASTING;

EID: 47849111521     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2007.4336229     Document Type: Conference Paper

References (3)

1. C. Kim et al., "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," Proc. Int'l. Symp. on Computer Architecture, 2005.
2. J. Huh et al., "A NUCA Substrate for Flexible CMP Cache Sharing," Proc. Int'l. Conf. on Supercomputing, 2005.
3. Standard Performance Evaluation Corporation, "SPEC CPU2000", http://www.spec.org/cpu/.