Uncorq: Unconstrained snoop request delivery in embedded-ring multiprocessors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 327-339

  Strauss, Karin ^a,c   Shen, Xiaowei ^b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IBM RESEARCH   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COHERENT LIGHT; ELECTRIC NETWORK TOPOLOGY; MULTIPROCESSING SYSTEMS;

CACHE COHERENCE; CHIP MULTI PROCESSOR (CMP); COHERENCE PROTOCOLS; COMMERCIAL APPLICATIONS; CONTROL MESSAGES; CRITICAL PATHS; INTERNATIONAL SYMPOSIUM; LOGICAL RING; MICRO ARCHITECTURES; MULTIPLE TRANSACTIONS; NETWORK PATHS; PERFORMANCE IMPROVEMENTS; PHYSICAL NETWORKS; PRE-FETCHING; UNIDIRECTIONAL RINGS;

NETWORK PROTOCOLS;

EID: 47349125701     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.37     Document Type: Conference Paper

References (17)

1. L. A. Barroso and M. Dubois. The Performance of Cache-Coherent Ring-Based Multiprocessors. In International Symposium on Computer Architecture, May 1993.
2. L. A. Barroso, K. Gharachorloo, and E. Bugnion. Memory System Characterization of Commercial Workloads. In International Symposium on Computer Architecture, June 1998.
3. J. F. Cantin, M. H. Lipasti, and J. E. Smith. Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. In International Symposium on Computer Architecture, June 2005.
4. P. Conway and B. Hughes. The AMD Opteron Northbridge Architecture, Present and Future. IEEE Micro Magazine, March/April 2007.
5. K. Gharachorloo, A. Gupta, and J. L. Hennessy. Two Techniques to Enhance the Performance of Memory Consistency Models. In International Conference on Parallel Processing, August 1991.
6. M. Martin, P. Harper, D. Sorin, M. Hill, and D. Wood. Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. In International Symposium on Computer Architecture, June 2003.
7. M. R. Marty and M. D. Hill. Coherence Ordering for Ring-Based Chip Multiprocessors. In International Symposium on Microarchitecture, December 2006.
8. A. Moshovos. RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. In International Symposium on Computer Architecture, June 2005.
9. A. Moshovos, G. Memik, B. Falsafi, and A. Choudhary. JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers. In International Symposium on High-Perfomance Computer Architecture, January 2001.
10. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, K. Strauss, S. Sarangi, P. Sack, and P. Montesinos. SESC Simulator, January 2005. http://sesc.sourceforge.net.
11. X. Shen, J. Huh, and B. Sinharoy. US Patent #7,266,642: Cache Residence Prediction, 2007.
12. E. Sikha, R. Simpson, C. May, and H. Warren. The PowerPC Architecture: A Specification for a New Family of RISC Processors. 1994.
13. K. Strauss. Cache Coherence in Embedded-Ring Multiprocessors. PhD thesis, University of Illinois at Urbana-Champaign, 2007.
14. K. Strauss, X. Shen, and J. Torrellas. Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. In International Symposium on Computer Architecture, June 2006.
15. J. M. Tendler, J. S. Dodson, J. S. Fields, H. Le, and B. Sinharoy. POWER4 System Microarchitecture. In IBM Journal of Research and Development, January 2002.
16. Virtutech. Virtutech Simics. http://www.virtutech.com/products.
17. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In International Symposium on Computer Architecture, June 1995.