A low-noise low-offset op amp in 0.35μm CMOS process

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn , Issue , 2006, Pages 624-627

  Zhineng, Zhu ^a   Tumati, Raghu ^a   Collins, Scott ^a   Smith, Rosemary ^a   Kotecki, David E ^a  

^a University of Maine   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

OPERATIONAL AMPLIFIERS; TELECOMMUNICATION SYSTEMS;

CMOS PROCESSING; DESIGN STRATEGIES; DIGITAL TRIMMING; FLICKER NOISES; HIGH SPEEDS; INTERNATIONAL CONFERENCES; LOW NOISE; LOW-OFFSET; UNITY GAIN BAND WIDTH;

PROCESS DESIGN;

EID: 47349124828     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379866     Document Type: Conference Paper

References (10)

1. J. G. Graeme, Photodiode Amplifiers:Op Amp Solutions. McGraw-Hill, 1995.
2. J. e. a. Heng, "The detection of dna using a silicon nanopore," IEEE International Electron Devices Meeting 2003, pp. 32.2.1-4, 2003.
3. "AD8099 data sheet," Norwood,MA, 2004.
4. J.-C. Bertails, "Low-frequency noise considerations for MOS amplifiers design," IEEE Journal of Solid-State Circuits, vol. SC-14, no. 4, pp. 773-776, Aug. 1979.
5. R. D. Jolly and R. H. McCharles, "A low-noise amplifier for switched capacitor filters," IEEE Journal of Solid-State Circuits, vol. SC-17, no. 6, pp. 1192-1194, Dec. 1982.
6. W. T. Holman and J. A. Connelly, "A compact low noise operational amplifier for a 1.2um digital cmos technology," IEEE Journal of Solid-State Circuits, vol. 30, no. 6, pp. 710-714, 1995.
7. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, 1996.
8. P. Chan, L. Ng, L. Siek, and K. Lau, "Designing CMOS folded-cascode operational amplifier with flicker noise minimisation," Microelectronics Journal, vol. 32, pp. 69-73, Jan. 2001.
9. H. T. S. James H. Atherton, "an offset reduction technique for use with cmos integrated comparators and amplifiers," IEEE Journal of Solid-State Circuits, vol. 27, no. 8, pp. 1168-1175, 1992.
10. P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, 2005.