Implications of false conflict rate trends for robust software transactional memory

Proceedings of the 2007 IEEE International Symposium on Workload Characterization, IISWC

Volumn , Issue , 2007, Pages 15-24

  Zilles, Craig ^a   Rajwar, Ravi ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; KETONES; POPULATION STATISTICS; TECHNICAL PRESENTATIONS;

ANALYTICAL MODELLING; BIRTHDAY PARADOX; CACHE BLOCKING; INTERNATIONAL SYMPOSIUM; LINEAR REDUCTION; NEGATIVE IMPACTS; PRACTICAL IMPLICATIONS; RATE TRENDS; ROBUST SOFTWARE; SOFTWARE TRANSACTIONAL MEMORY; TRANSACTIONAL MEMORY (TM); WORKLOAD CHARACTERIZATION;

STORAGE ALLOCATION (COMPUTER);

EID: 47349114921     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2007.4362177     Document Type: Conference Paper

References (23)

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