Checking safety by inductive generalization of counterexamples to induction

Proceedings - Formal Methods in Computer Aided Design, FMCAD 2007

Volumn , Issue , 2007, Pages 173-180

  Bradley, Aaron R ^a   Manna, Zohar ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS TIME; EXPERIMENTAL DATA; FINITE STATE SYSTEMS; HARD PROBLEMS; LARGE CIRCUITS; SAFETY ANALYSIS; SAFETY SPECIFICATIONS; STATE SPACES;

ABSTRACTING; COMPUTER AIDED DESIGN; STATE SPACE METHODS;

FORMAL METHODS;

EID: 47349093657     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FAMCAD.2007.15     Document Type: Conference Paper

References (21)

1. Z. Manna and A. Pnueli, Temporal Verification of Reactive Systems: Safety. New York: Springer-Verlag, 1995.
2. P. Cousot and R. Cousot, "Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints," in POPL. ACM Press, 1977, pp. 238-252.
3. B. Knaster, "Un theoreme sur les fonctions d'ensembles," Ann. Soc. Polon. Math., vol. 6, pp. 133-134, 1928.
4. A. Tarski, "A lattice-theoretical fixpoint theorem and its applications," Pacific Journal of Mathematics, vol. 5, no. 2, pp. 285-309, 1955.
5. K. L. McMillan, "Applying SAT methods in unbounded symbolic model checking." in CAV, ser. LNCS, vol. 2404. Springer, 2002, pp. 250-264.
6. H. Jin and F Somenzi, "Prime clauses for fast enumeration of satisfying assignments to boolean circuits," in DAC. ACM Press, 2005.
7. L. de Moura, H. Ruess, and M. Sorea, "Bounded model checking and induction: From refutation to verification," in CAV, ser. LNCS. Springer, 2003.
8. V. C. Vimjam and M. S. Hsiao, "Fast illegal state identification for improving SAT-based induction," in DAC. ACM Press, 2006.
9. M. Awedh and F Somenzi, "Automatic invariant strengthening to prove properties in bounded model checking," in DAC. ACM Press, 2006.
10. M. W. Moskewicz, C. F Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in DAC, 2001.
11. K. L. McMillan and N. Amla, "Automatic abstraction without counterexamples." in TACAS, ser. LNCS, vol. 2619. Springer, 2003, pp. 2-17.
12. K. L. McMillan, "Interpolation and SAT-based model checking," in CAV, ser. LNCS, vol. 2725. Springer, 2003, pp. 1-13.
13. _, "Applications of Craig interpolants in model checking." in TACAS, ser. LNCS, vol. 3440. Springer, 2005, pp. 1-12.
14. VIS. [Online]. Available: http://visi.colorado.edu/~vis
15. A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic model checking without BDDs," in TACAS. Springer, 1999, pp. 193-207.
16. M. Sheeran, S. Singh, and G. Stalmarck, "Checking safety properties using induction and a SAT-solver," in FMCAD, ser. LNCS, vol. 1954. Springer, 2000.
17. R. Armoni, L. Fix, R. Fraer, S. Huddleston, N. Piterman, and M. Vardi, "SAT-based induction for temporal safety properties," in BMC, 2004.
18. E. Clarke, O. Grumberg, S. Jha, Y. Lu, and H. Veith, " Counterexample-guided abstraction refinement for symbolic model checking," J. ACM, vol. 50, no. 5, pp. 752-794, 2003.
19. H. Jain, D. Kroening, N. Sharygina, and E. M. Clarke, "Word level predicate abstraction and refinement for verifying RTL verilog." in DAC, 2005.
20. A. Zeller, "Yesterday, my program worked. Today, it does not. Why?" in ESEC / SIGSOFT FSE, 1999, pp. 253-267.
21. A. R. Bradley and Z. Manna, "Verification constraint problems with strengthening," in ICTAC, ser. LNCS, vol. 3722. Springer, 2006.