Modeling of multi-layer nanocrystal memory

65th DRC Device Research Conference

Volumn , Issue , 2007, Pages 221-222

  Hou, Tuo Hung ^a   Lee, Chungho ^a   Kan, Ldwin C ^a  

^a School of Operations Research and Industrial Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 47249143399     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2007.4373727     Document Type: Conference Paper

References (4)

1. R. Ohba et. al., IEEE Trans. Electron Devices, vol. 49, p. 1392, 2002.
2. C. Lee et. al., IEDM Tech. Dig, 2003, p. 557.
3. T.-H Hou et. al., IEEE Trans. Electron Devices, vol. 53, p. 3095, 2006.
4. R. Ohba et. al., IEDM Tech. Dig., 2006, p. 959.