Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 66-67

  Kadoshima, M ^a   Sugita, Y ^a   Shiraishi, K ^b   Watanabe, H ^c   Ohta, A ^d   Miyazaki, S ^d   Nakajima, K ^e   Chikyow, T ^e   Yamada, K ^f   Aminaka, T ^a   Kurosawa, E ^a   Matsuki, T ^a   Aoyama, T ^a   Nara, Y ^a   Ohji, Y ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b UNIVERSITY OF TSUKUBA   (Japan)

^c OSAKA UNIVERSITY   (Japan)

^d HIROSHIMA UNIVERSITY   (Japan)

^e National Institute for Material Science

^f WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; ANNEALING; COST EFFECTIVENESS; FERMIONS; FIELD EFFECT TRANSISTORS; HAFNIUM; MESFET DEVICES; METALS; MODULATION; NONMETALS; OXYGEN; TECHNOLOGY; WEAR RESISTANCE;

ANNEALING PROCESSING; CMOS TECHNOLOGIES; ELECTRICAL CHARACTERISTICS; FERMI LEVEL PINNING; HIGH-TEMPERATURE ANNEALING; METAL GATES; OXYGEN INTERSTITIALS; SYSTEMATIC (CO); VLSI TECHNOLOGIES;

OXYGEN VACANCIES;

EID: 47249129868     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339729     Document Type: Conference Paper

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