1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 26-27

  Sakoda, Tsunehisa ^a   Tamura, Naoyoshi ^a   Xiao, Shiqin ^a   Minakata, Hiroshi ^a   Morisaki, Yusuke ^a   Nishigaya, Keita ^a   Saiki, Takashi ^a   Uetake, Toshiyuki ^a   Iwasaki, Toshio ^a   Ehara, Hideo ^a   Matsuyama, Hideya ^a   Shimizu, Hiroshi ^a   Hashimoto, Koichi ^a   Kimoto, Masayoshi ^a   Kase, Masataka ^a   Ikeda, Kazuto ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC RANDOM ACCESS STORAGE;

CURRENT FLUCTUATIONS; GATE CURRENTS; VLSI TECHNOLOGIES;

RISK ASSESSMENT;

EID: 47249127191     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339713     Document Type: Conference Paper

References (6)

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4. S. Nakai et al., Symp. on VLSI Tech 2002, pp.66-67
5. H. Mori et al., SSDM 2004, pp.710-711
6. A. Ghetti, Microelectronic Eng. 59 (2001) pp.127-136