Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing

SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2005, Pages 149-153

  Gagliolo, Sergio ^a,b   Pruzzo, Giacomo ^a   Caviglia, Daniele D ^a,b  

^a UNIVERSITY OF GENOA   (Italy)

^b IEEE

Author keywords

CMOS; Low power; Low voltage; Phase noise; Resistor biasing; Voltage Controlled Oscillator (VCO); Wireless

Indexed keywords

COMPETITION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); NOISE FIGURE; RESISTORS; STANDARDS; SYSTEMS ANALYSIS; TELECOMMUNICATION; VARIABLE FREQUENCY OSCILLATORS;

1.8 GHZ; CIRCUIT TOPOLOGIES; CMOS VCO; CROSS-COUPLED; CURRENT MIRRORING; DESIGN CHALLENGES; DEVICE NOISE; HIGH PERFORMANCE; IC ARCHITECTURES; LOW-PHASE-NOISE; MODERN STANDARDS; NOISE LEVELS; NOISE PERFORMANCES; OFFSET FREQUENCIES; PORTABLE SYSTEMS; POWER CONSUMPTION (CE); SPECTRAL PURITY; SUPPLY VOLTAGES; SYSTEMS DESIGN; TAIL CURRENT SOURCE; TAIL CURRENTS; TUNING RANGE (TR); VOLTAGE-CONTROLLED OSCILLATOR (VCO); WIRELESS (WIFI) COMMUNICATION; WIRELESS STANDARDS;

PHASE NOISE;

EID: 46449086779     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2005.4286848     Document Type: Conference Paper

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