Programming Models for Hybrid CPU/FPGA Chips

Computer

Volumn 37, Issue 1, 2004, Pages 118-120

  Andrews, David ^a   Niehaus, Douglas ^a   Ashenden, Peter ^b  

^a UNIVERSITY OF KANSAS   (United States)

^b Ashenden Designs   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

MULTITHREAD PROGRAMMING; THREAD SCHEDULERS;

ABSTRACTING; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SOFTWARE; COSTS; DATA STRUCTURES; FIELD PROGRAMMABLE GATE ARRAYS; INDUSTRIAL ECONOMICS; LOGIC GATES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PUBLIC POLICY; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

EMBEDDED SYSTEMS;

EID: 0742285889     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2004.1260732     Document Type: Review

References (0)