Solder paste printing and stencil design considerations for wafer bumping

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn 29, Issue , 2004, Pages 229-237

  Lathrop, Richard ^a  

^a Heraeus Ind Circt Mat Division   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SOLDER PASTE; STENCIL PRINTING PROCESS; STENCIL THICKNESS; WAFER BUMPING;

ELECTROPLATING; INTERFACIAL ENERGY; OSCILLATIONS; REAL TIME SYSTEMS; SOLDERING; SPUTTERING; THICKNESS CONTROL; X RAY ANALYSIS;

WSI CIRCUITS;

EID: 4644256891     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Prismark Partners LLC, The Electronics Industry Report, (New York 2003), pp 139-144
2. Jackson, G.J. et al, 'Differences in the Sub-Processes on Ultra Fine Pitch Stencil Printing due to Type-6 and Type-7 Pb-free Solder Pastes used for Flip Chip," Electronics Components and Technology Conference, (2003), pp. 536-543.
3. Johnson, A., "Tutorial: How to Select the Best Stencil for SMT and Advanced IV Package Printing," Chip Scale Review, (April 2003), pp. 51-57.
4. Lathrop, R.R., "Optimizing Solder Paste printing For Wafer Bumping," APEX West Conference, (February 2004).
5. Coleman, W.E., "Stencil Design and Performance for Flip Chip/Wafer Bumping," APEX West Conference, (February 2004).